WOF Enablement in PGPE

    -Full functionality for OCC Start/Stop, Set PMCR, Clip Updt
    -New code structure for PGPE(actuate/process thread, etc)
    -Update CME code as per the new Doorbell0
    -Added place holders for SGPE-PGPE IPCs
    -Place holders for Error Interrupts like OCB_Error, XSTOP
    -Added code to correctly account for VRM transition delays

Change-Id: I301b14304677e2ed0130f1c3479d523dcb931293
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34156
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34157
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 21 insertions, 3 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
index 6b43819bd..fd4ce8da0 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -218,13 +218,31 @@ typedef struct
     /// Resonant Clock Grid Management Setup
     ResonantClockingSetup resclk;
 
-    //Voltage change step size
-    uint32_t ext_vdd_step_size_mv;
+    //Time b/w ext VRM detects write voltage cmd and when voltage begins to move
+    uint32_t ext_vrm_transition_start_ns;
 
+    //Transition rate for an increasing VDD voltage excursion
+    uint32_t ext_vrm_transition_rate_inc_uv_per_us;
+
+    //Transition rate for an decreasing VDD voltage excursion
+    uint32_t ext_vrm_transition_rate_dec_uv_per_us;
+
+    //Delay to account for VDD rail setting
+    uint32_t ext_vrm_stabilization_time_us;
+
+    //External VRM transition step size
+    uint32_t ext_vrm_step_size_mv;
+
+    //Nest frequency in Mhz. This is used by FIT interrupt
     uint32_t nest_frequency_mhz;
 
+    //Precalculated Pstate-Voltage Slopes
     uint16_t PsVSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
+
+    //Precalculated Voltage-Pstates Slopes
     uint16_t VPsSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
+
+
     // @todo DPLL Droop Settings.  These need communication to SGPE for STOP
 
 } GlobalPstateParmBlock;