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author | Prem Shanker Jha <premjha2@in.ibm.com> | 2019-03-28 04:40:12 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-08 14:55:40 -0500 |
commit | 58df73fd107419526422d2075e5085253a5202d2 (patch) | |
tree | c2901f959914684411ab59d295fbfa72521dc1d2 /src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h | |
parent | c5e2251b0c17916310b54cbf96540ffca1f4b1f7 (diff) | |
download | talos-hostboot-58df73fd107419526422d2075e5085253a5202d2.tar.gz talos-hostboot-58df73fd107419526422d2075e5085253a5202d2.zip |
VDM(Part 3): Image build changes for quad level VDM
Commit accomplishes following:
- enables CME booting using new CPMR layout
- copies new definition of poundw to LPSPB
- enables quad level LPSPB
- implements new CPMR layout that supports customized LPSPB.
- for old VPD version, retains old CPMR layout
Change-Id: I66a13579e0edbc046226db259a736416e1e5c268
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75272
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75278
Reviewed-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h index d7739af81..373bd8d8d 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h @@ -35,6 +35,7 @@ #define __P9_PSTATES_CME_H__ #include <p9_pstates_common.h> +#include <p9_hcd_memmap_base.H> /// @} @@ -161,6 +162,23 @@ typedef struct uint16_t r_core_header; } resistance_entry_t; +typedef struct __attribute__((packed)) +{ + uint16_t r_package_common; + uint16_t r_quad; + uint16_t r_core; + uint16_t r_quad_header; + uint16_t r_core_header; + uint8_t r_vdm_cal_version; + uint8_t r_avg_min_scale_fact; + uint16_t r_undervolt_vmin_floor_limit; + uint8_t r_min_bin_protect_pc_adder; + uint8_t r_min_bin_protect_bin_adder; + uint8_t r_undervolt_allowed; + uint8_t reserve[10]; +} +resistance_entry_per_quad_t; + typedef struct { poundw_entry_t poundw[NUM_OP_POINTS]; @@ -178,6 +196,35 @@ typedef struct PoundW_data vpd_w_data; } LP_VDMParmBlock; +typedef struct __attribute__((packed)) +{ + uint16_t ivdd_tdp_ac_current_10ma; + uint16_t ivdd_tdp_dc_current_10ma; + uint8_t vdm_overvolt_small_thresholds; + uint8_t vdm_large_extreme_thresholds; + uint8_t vdm_normal_freq_drop; // N_S and N_L Drop + uint8_t vdm_normal_freq_return; // L_S and S_N Return + uint8_t vdm_vid_compare_per_quad[MAX_QUADS_PER_CHIP]; + uint8_t vdm_cal_state_avg_min_per_quad[MAX_QUADS_PER_CHIP]; + uint16_t vdm_cal_state_vmin; + uint8_t vdm_cal_state_avg_core_dts; + uint16_t vdm_cal_state_avg_core_current; + uint16_t vdm_spare; +} +poundw_entry_per_quad_t; + +typedef struct __attribute__((packed)) +{ + poundw_entry_per_quad_t poundw[NUM_OP_POINTS]; + resistance_entry_per_quad_t resistance_data; +} +PoundW_data_per_quad; + + +typedef struct +{ + PoundW_data_per_quad vpd_w_data; +} LP_VDMParmBlock_PerQuad; /// The layout of the data created by the Pstate table creation firmware for /// comsumption by the Pstate GPE. This data will reside in the Quad |