SMF: SBE updates for SMF (URMOR set and CPMMR[Runtime Wakeup Mode] clear)

- set URMOR if MSR[S] bit is set in p9_sbe_load_bootloader
- clear CPMMR[Runtime Wakeup Mode] in all cores in p9_sbe_select_ex to ensure
  Hostboot starts from known state

Change-Id: I572a1d9e0ebf8e194c811e2b8c176d145b7361e3
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61812
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61818
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
index cbbb0eead..5f3ebba57 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
@@ -168,6 +168,8 @@ enum PM_CPPM_CSAR_DEFS
 enum PM_PPM_FW_FLAGS
 {
     CPPM_CPMMR_DISABLE_PERIODIC_CORE_QUIESCE = 2,
+    CPPM_CPMMR_RUNTIME_WAKEUP_MODE           = 3,
+    CPPM_CPMMR_WAKEUP_ERROR_INJECT_MODE      = 8,
     QPPM_QCCR_IGNORE_QUAD_STOP_EXITS        = 10,
     QPPM_QCCR_IGNORE_QUAD_STOP_ENTRIES      = 11
 };