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| author | Adam Hale <adam.samuel.hale@ibm.com> | 2017-07-21 00:44:21 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-05 21:22:15 -0400 |
| commit | d926863f798c1d881d2db68b4f64f60378d7d816 (patch) | |
| tree | 06677117cb531982e98fb7d123bc83db065d9a9a /src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | |
| parent | 0cd2d4c3338d6222c271d78088dbf8ba5381d5bd (diff) | |
| download | talos-hostboot-d926863f798c1d881d2db68b4f64f60378d7d816.tar.gz talos-hostboot-d926863f798c1d881d2db68b4f64f60378d7d816.zip | |
Characterization Default Image
Change-Id: I24ce2816a6e5583824f94db4f200cba9e0a2ec74
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43407
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43410
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index ee7f48d33..76954c274 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -198,6 +198,8 @@ HCD_HDR_UINT32(g_ppmr_pgpe_sram_img_size, 0); // PGPE Actual SRAM Image Size HCD_HDR_UINT32(g_ppmr_pgpe_boot_prog_code, 0 );// for debug of PGPE booting HCD_HDR_UINT32(g_ppmr_wof_table_offset, 0 ); // Offset to start of WOF Table HCD_HDR_UINT32(g_ppmr_wof_table_length, 0 ); // Length of WOF table +HCD_HDR_UINT32(g_ppmr_aux_task_offset, 0 ); // PGPE Aux Task Offset +HCD_HDR_UINT32(g_ppmr_aux_task_length, 0 ); // PGPE Aux Task Length HCD_HDR_PAD(0x200); #ifdef __ASSEMBLER__ .endm @@ -327,17 +329,17 @@ typedef struct { #endif HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER); // PGPE_1.0 -HCD_HDR_UINT32(g_pgpe_sys_reset_addr, 0 ); // Fully qualified OCC address where pk_init resides -HCD_HDR_UINT32(g_pgpe_shared_sram_addr, 0 ); // SRAM address where shared SRAM begins -HCD_HDR_UINT32(g_pgpe_ivpr_addr, 0 ); // Beginning of PGPE region in OCC SRAM -HCD_HDR_UINT32(g_pgpe_shared_sram_len, 0 ); // Length of shared SRAM area -HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PGPE Image -HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version -HCD_HDR_UINT16(g_pgpe_flags, 0 ); // PGPE Flags -HCD_HDR_UINT16(g_pgpe_reserve1, 0 ); // Reserve field -HCD_HDR_UINT32(g_pgpe_reserve2, 0 ); // Reserve field -HCD_HDR_UINT32(g_pgpe_gppb_sram_addr, 0 ); // Offset to Global P State Parameter Block -HCD_HDR_UINT32(g_pgpe_hcode_length, 0 ); // Length of PGPE Hcode +HCD_HDR_UINT32(g_pgpe_sys_reset_addr, 0 ); // Fully qualified OCC address where pk_init resides +HCD_HDR_UINT32(g_pgpe_shared_sram_addr, 0 ); // SRAM address where shared SRAM begins +HCD_HDR_UINT32(g_pgpe_ivpr_addr, 0 ); // Beginning of PGPE region in OCC SRAM +HCD_HDR_UINT32(g_pgpe_shared_sram_len, 0 ); // Length of shared SRAM area +HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PGPE Image +HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version +HCD_HDR_UINT16(g_pgpe_flags, 0 ); // PGPE Flags +HCD_HDR_UINT16(g_pgpe_reserve1, 0 ); // Reserve field +HCD_HDR_UINT32(g_pgpe_reserve2, 0 ); // Reserve field +HCD_HDR_UINT32(g_pgpe_gppb_sram_addr, 0 ); // Offset to Global P State Parameter Block +HCD_HDR_UINT32(g_pgpe_hcode_length, 0 ); // Length of PGPE Hcode HCD_HDR_UINT32(g_pgpe_gppb_mem_offset, 0 ); // Offset to start of Global PS Param Block wrt start of HOMER. HCD_HDR_UINT32(g_pgpe_gppb_length, 0 ); // Length of Global P State Parameter Block @@ -620,6 +622,7 @@ typedef struct uint8_t l1BootLoader[PGPE_BOOT_COPIER_SIZE]; uint8_t l2BootLoader[PGPE_BOOT_LOADER_SIZE]; uint8_t pgpeSramImage[PGPE_IMAGE_SIZE]; // Includes the Global Pstate Parameter Block + uint8_t aux_task[PGPE_AUX_TASK_SIZE]; uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE]; uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)]; |
