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| author | Yue Du <daviddu@us.ibm.com> | 2016-11-17 00:32:33 -0600 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-12-16 12:30:06 -0500 |
| commit | 294e4d770414f943fed4ca165488c0260517b43a (patch) | |
| tree | aca69ddad6d8ecea95b702b22e1466afc29ef198 /src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | |
| parent | 79ed124c9312189f52d01eff96eec1ddc673200e (diff) | |
| download | talos-hostboot-294e4d770414f943fed4ca165488c0260517b43a.tar.gz talos-hostboot-294e4d770414f943fed4ca165488c0260517b43a.zip | |
STOP: enable cme trace array before cme boot in SGPE
Change-Id: If54189d3fcb17cb3b59019c62eb389ef01fc58cb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32749
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33432
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 135309866..d336bc456 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -176,7 +176,8 @@ HCD_HDR_UINT32(g_sgpe_ivpr_address, 0); HCD_HDR_UINT32(g_sgpe_reserve2, 0); HCD_HDR_UINT32(g_sgpe_build_date, 0); HCD_HDR_UINT32(g_sgpe_build_ver, 0); -HCD_HDR_UINT64(g_sgpe_reserve_flags, 0); +HCD_HDR_UINT32(g_sgpe_reserve_flags, 0); +HCD_HDR_UINT32(g_sgpe_reserve3, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_ovrd_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); |
