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author | Yue Du <daviddu@us.ibm.com> | 2015-12-04 15:37:19 -0600 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-02-27 11:36:21 -0500 |
commit | d2f8541b5122b614aa377d826176b6e65a60d9a4 (patch) | |
tree | a64e007e4fa4ad9155e266ee3ef82f84f52003c7 /src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H | |
parent | 6da3ac3c8f95c3e60a9586bf18ec1ed4d6a8a933 (diff) | |
download | talos-hostboot-d2f8541b5122b614aa377d826176b6e65a60d9a4.tar.gz talos-hostboot-d2f8541b5122b614aa377d826176b6e65a60d9a4.zip |
HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34
Change-Id: Iff858d6a97c75e8b9477ee860aca9e7d2ca96478
Original-Change-Id: Ia88b64463b0b911aa0882db20b85eda7a30571d6
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22225
Tested-by: Jenkins Server
Tested-by: PPE CI
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37032
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H | 63 |
1 files changed, 53 insertions, 10 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H index 274f31286..8f692f028 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H @@ -43,9 +43,22 @@ // Create a multi-bit mask of \a n bits starting at bit \a b #define BITS64(b, n) ((0xffffffffffffffffull << (64 - (n))) >> (b)) +#define BITS32(b, n) ((0xffffffff << (32 - (n))) >> (b)) +#define BITS16(b, n) ((0xffff << (16 - (n))) >> (b)) +#define BITS8(b, n) ((0xff << (8 - (n))) >> (b)) // Create a single bit mask at bit \a b #define BIT64(b) BITS64((b), 1) +#define BIT32(b) BITS32((b), 1) +#define BIT16(b) BITS16((b), 1) +#define BIT8(b) BITS8((b), 1) + +// Create a amount of shift to bit location \a b +#define SHIFT64(b) (63-b) +#define SHIFT32(b) (31-b) +#define SHIFT16(b) (15-b) +#define SHIFT8(b) (7-b) + // The BUF_* macros apply operations to a newly constructed buffer #define BUF_SET(bit) fapi2::buffer<uint64_t>().setBit<bit>() @@ -54,7 +67,6 @@ fapi2::buffer<uint64_t>().insertFromRight<start,size>(val) #define BUF_REPLACE(start,size,val) \ fapi2::buffer<uint64_t>().flush<1>().insertFromRight<start,size>(val) - // The following DATA_* and MASK_* macros assume you have // "fapi2::buffer<uint64_t> l_data64" declared @@ -87,6 +99,22 @@ namespace p9hcd { +// Bit masks used by CME hcode +enum P9_HCD_CME_CORE_MASKS +{ + LEFT_CORE = 0x2, + RIGHT_CORE = 0x1, + BOTH_CORES = 0x3, + NO_CORE = 0x0 +}; + +// Control parameters for PCB Aribter +enum P9_HCD_PCB_ARBITER_CTRL +{ + REQUEST_ARBITER = 1, + RELEASE_ARBITER = 0 +}; + // Constants to calculate hcd poll timeout intervals enum P9_HCD_COMMON_TIMEOUT_CONSTANTS { @@ -117,6 +145,7 @@ enum P9_HCD_COMMON_CLK_CTRL_CONSTANTS CLK_START_CMD = BIT64(1), CLK_SLAVE_MODE = BIT64(2), CLK_MASTER_MODE = BIT64(3), + CLK_REGION_ANEP = BIT64(10), CLK_REGION_DPLL = BIT64(14), CLK_REGION_L2 = BITS64(8, 2), CLK_REGION_ALL_BUT_DPLL_L2 = BITS64(4, 4) | BITS64(10, 4), @@ -129,21 +158,25 @@ enum P9_HCD_COMMON_CLK_CTRL_CONSTANTS enum P9_HCD_COMMON_CLK_CTRL_VECTORS { CLK_START_REGION_ALL_THOLD_NSL_ARY = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_ALL | CLK_THOLD_NSL_ARY), + (CLK_START_CMD | CLK_REGION_ALL | CLK_THOLD_NSL_ARY), CLK_START_REGION_ALL_THOLD_ALL = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_ALL | CLK_THOLD_ALL), + (CLK_START_CMD | CLK_REGION_ALL | CLK_THOLD_ALL), CLK_START_REGION_ALL_BUT_DPLL_L2_THOLD_NSL_ARY = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_ALL_BUT_DPLL_L2 | CLK_THOLD_NSL_ARY), + (CLK_START_CMD | CLK_REGION_ALL_BUT_DPLL_L2 | CLK_THOLD_NSL_ARY), CLK_START_REGION_ALL_BUT_DPLL_L2_THOLD_ALL = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_ALL_BUT_DPLL_L2 | CLK_THOLD_ALL), + (CLK_START_CMD | CLK_REGION_ALL_BUT_DPLL_L2 | CLK_THOLD_ALL), CLK_START_REGION_L2_THOLD_NSL_ARY = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_L2 | CLK_THOLD_NSL_ARY), + (CLK_START_CMD | CLK_REGION_L2 | CLK_THOLD_NSL_ARY), CLK_START_REGION_L2_THOLD_ALL = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_L2 | CLK_THOLD_ALL), + (CLK_START_CMD | CLK_REGION_L2 | CLK_THOLD_ALL), CLK_START_REGION_DPLL_THOLD_NSL_ARY = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_DPLL | CLK_THOLD_NSL_ARY), + (CLK_START_CMD | CLK_REGION_DPLL | CLK_THOLD_NSL_ARY), CLK_START_REGION_DPLL_THOLD_ALL = - (CLK_START_CMD | CLK_MASTER_MODE | CLK_REGION_DPLL | CLK_THOLD_ALL) + (CLK_START_CMD | CLK_REGION_DPLL | CLK_THOLD_ALL), + CLK_START_REGION_ANEP_THOLD_NSL_ARY = + (CLK_START_CMD | CLK_REGION_ANEP | CLK_THOLD_NSL_ARY), + CLK_START_REGION_ANEP_THOLD_ALL = + (CLK_START_CMD | CLK_REGION_ANEP | CLK_THOLD_ALL) }; // SCAN0 Constants @@ -151,12 +184,16 @@ enum P9_HCD_COMMON_SCAN0_CONSTANTS { SCAN0_REGION_ALL = 0x7FF, SCAN0_REGION_ALL_BUT_PLL = 0x7FE, + SCAN0_REGION_ALL_BUT_ANEP_PLL = 0x7EE, SCAN0_REGION_PLL = 0x001, + SCAN0_REGION_DPLL_ANEP = 0x011, SCAN0_REGION_CORE_ONLY = 0x300, + SCAN0_REGION_PERV_CORE = 0x700, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME = 0xDCF, SCAN0_TYPE_GPTR_REPR_TIME = 0x230, SCAN0_TYPE_REPR_TIME = 0x030, SCAN0_TYPE_GPTR = 0x200, + SCAN0_TYPE_FUNC = 0x800, SCAN0_TYPE_FUNC_BNDY = 0x808 }; //OCC FLag defines @@ -191,6 +228,7 @@ enum XCR_DEFS /// @todo needs to review this /// SCAN Repeats(from P8) +/* #define GENERIC_CC_SCAN0_MAXIMUM 8191 #define SCAN0_FUNC_FLUSH_LENGTH 8000 #define SCAN0_GPTR_FLUSH_LENGTH 14000 @@ -198,10 +236,15 @@ enum XCR_DEFS ((SCAN0_FUNC_FLUSH_LENGTH / GENERIC_CC_SCAN0_MAXIMUM)+1) #define P9_HCD_SCAN_GPTR_REPEAT \ ((SCAN0_GPTR_FLUSH_LENGTH / GENERIC_CC_SCAN0_MAXIMUM)+1) +*/ +#define P9_HCD_SCAN_FUNC_REPEAT 40 +#define P9_HCD_SCAN_GPTR_REPEAT 40 /// @todo remove these once correct header contains them /// Scom addresses missing from p9_quad_scom_addresses.H -#define EQ_QPPM_QCCR_WCLEAR 0x100F01BE #define EQ_QPPM_QCCR_WOR 0x100F01BF +#define CME_LCL_SICR_OR 0xc0000510 +#define CME_LCL_SICR_CLR 0xc0000518 +#define CME_LCL_SISR 0xc0000520 #endif // __P9_HCD_COMMON_H__ |