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| author | Yue Du <daviddu@us.ibm.com> | 2017-09-21 09:15:06 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-10-03 00:00:36 -0400 |
| commit | 2f10d5e8ef8ddcefd180bddce78d315f9a9961bf (patch) | |
| tree | 4f551ddf1400ee6c2fc913988a345705b70e7112 /src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H | |
| parent | 7493c1cdd21c8fde5ed4ae78f7235798a819373f (diff) | |
| download | talos-hostboot-2f10d5e8ef8ddcefd180bddce78d315f9a9961bf.tar.gz talos-hostboot-2f10d5e8ef8ddcefd180bddce78d315f9a9961bf.zip | |
STOP: Properly clear DPLL unlock indication in dpll_setup
Change-Id: I0d8ecd45e3b4f7414de10bb785069509b623f7ab
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46563
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46877
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H index e1a24fb62..c65f549e8 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H @@ -528,6 +528,17 @@ p9_common_poweronoff( FAPI_DBG("Assert vital thold via NET_CTRL0[16]"); FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(16))); + if (l_type == 1) + { + // upon power off cache, dpll is about to be unlocked + // to prevent pcb fir fires, need to mask the bit for the time being + // the error will be cleared and unmasked when dpll is locked again + FAPI_DBG("Mask DPLL unlock error in FIR via SLAVE_CONFIG[12]"); + FAPI_TRY(getScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64)); + l_data64.setBit<12>(); + FAPI_TRY(putScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64));// + } + /////////////////////////////////////////////////////////////////////////// // Procedure code /////////////////////////////////////////////////////////////////////////// |
