Run dmi dccal and linktrain on all channels at once.

Change-Id: I25d382491639a3646ac5948c2c2a0502d0cfb6ab
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43051
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45335
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

4 files changed, 183 insertions, 76 deletions

diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C
index 6c173943c..68e36b3f8 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.C
@@ -70,6 +70,13 @@
 fapi2::ReturnCode tx_zcal_run_bus(const DMI_TGT i_tgt);
 
 /**
+ * @brief Tx Z Impedance Calibration State Machine
+ * @param[in] i_tgt FAPI2 Target
+ * @retval ReturnCode
+ */
+fapi2::ReturnCode tx_zcal_run_bus_poll(const DMI_TGT i_tgt);
+
+/**
  * @brief Tx Z Impedance Calibration
  * @param[in] i_tgt  FAPI2 Target
  * @retval ReturnCode
@@ -97,28 +104,69 @@ fapi2::ReturnCode rx_dccal_start_grp(const DMI_TGT i_tgt);
 /**
  * @brief A I/O EDI+ Procedure that runs Rx Dccal and Tx Z Impedance calibration
  * on every EDI+ DMI Chiplet.
- * @param[in] i_tgt  Reference to DMI Target
+ * @param[in] i_target_chip  Chip target
  * @return FAPI2_RC_SUCCESSS on success, error otherwise
  */
-fapi2::ReturnCode p9_io_dmi_dccal(const DMI_TGT& i_tgt)
+fapi2::ReturnCode p9_io_dmi_dccal(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
+    const uint64_t DLY_20MS         = 20000000;
+    const uint64_t DLY_10MIL_CYCLES = 10000000;
+    const uint64_t DLY_100MS         = 100000000;
+    const uint64_t DLY_1MIL_CYCLES  = 1000000;
+
     FAPI_IMP("p9_io_dmi_dccal: I/O EDI+ Dmi Entering");
 
     char l_tgtStr[fapi2::MAX_ECMD_STRING_LEN];
-    fapi2::toString(i_tgt, l_tgtStr, fapi2::MAX_ECMD_STRING_LEN);
-    FAPI_DBG("I/O EDI+ Dmi Dccal %s", l_tgtStr);
 
-    // Runs Tx Zcal on a per bus basis
-    FAPI_TRY(tx_zcal_run_bus(i_tgt), "I/O Edi+ Dmi Tx Z-Cal Run Bus Failed");
+    for (auto l_tgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        if (!l_tgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>().empty())
+        {
+            fapi2::toString(l_tgt, l_tgtStr, fapi2::MAX_ECMD_STRING_LEN);
+            FAPI_DBG("I/O EDI+ Dmi Dccal %s", l_tgtStr);
 
-    // Sets Tx Zcal Group Settings based on the bus results
-    FAPI_TRY(tx_zcal_set_grp(i_tgt), "I/O Edi+ Dmi Tx Z-Cal Set Grp Failed");
+            // Runs Tx Zcal on a per bus basis
+            FAPI_TRY(tx_zcal_run_bus(l_tgt), "I/O Edi+ Dmi Tx Z-Cal Run Bus Failed");
+        }
+    }
 
-    // Starts Rx Dccal on a per group basis
-    FAPI_TRY(rx_dccal_start_grp(i_tgt), "I/O Edi+ Dmi Rx DC Cal Start Failed");
+
+    // Delay before we start polling.  20ms was use from past p8 learning
+    FAPI_TRY(fapi2::delay(DLY_20MS, DLY_10MIL_CYCLES));
+
+    for (auto l_tgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        if (!l_tgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>().empty())
+        {
+            // Runs Tx Zcal on a per bus basis
+            FAPI_TRY(tx_zcal_run_bus_poll(l_tgt), "I/O Edi+ Dmi Tx Z-Cal Run Bus Failed");
+        }
+    }
+
+    for (auto l_tgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        if (!l_tgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>().empty())
+        {
+            // Sets Tx Zcal Group Settings based on the bus results
+            FAPI_TRY(tx_zcal_set_grp(l_tgt), "I/O Edi+ Dmi Tx Z-Cal Set Grp Failed");
+
+            // Starts Rx Dccal on a per group basis
+            FAPI_TRY(rx_dccal_start_grp(l_tgt), "I/O Edi+ Dmi Rx DC Cal Start Failed");
+        }
+    }
+
+    // Delay before we start polling.  100ms was use from past p8 learning
+    FAPI_TRY(fapi2::delay(DLY_100MS, DLY_1MIL_CYCLES),
+             "rx_dc_cal_poll: Fapi Delay Failed.");
 
     // Checks/polls Rx Dccal on a per group basis
-    FAPI_TRY(rx_dccal_poll_grp(i_tgt), "I/O Edi+ Dmi Rx DC Cal Poll Failed");
+    for (auto l_tgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        if (!l_tgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>().empty())
+        {
+            FAPI_TRY(rx_dccal_poll_grp(l_tgt), "I/O Edi+ Dmi Rx DC Cal Poll Failed");
+        }
+    }
 
 fapi_try_exit:
 
@@ -214,14 +262,8 @@ fapi2::ReturnCode tx_zcal_verify_results(
  */
 fapi2::ReturnCode tx_zcal_run_bus(const DMI_TGT i_tgt)
 {
-    const uint64_t DLY_20MS         = 20000000;
-    const uint64_t DLY_10US         = 10000;
-    const uint64_t DLY_10MIL_CYCLES = 10000000;
-    const uint64_t DLY_1MIL_CYCLES  = 1000000;
-    const uint32_t TIMEOUT          = 200;
     const uint8_t GRP3              = 3;
     const uint8_t LN0               = 0;
-    uint32_t l_count                = 0;
     uint64_t l_data                 = 0;
     uint8_t       l_is_sim = 0;
 
@@ -246,8 +288,26 @@ fapi2::ReturnCode tx_zcal_run_bus(const DMI_TGT i_tgt)
     // The Done bit is read only pulse, must use pie driver or system model in sim
     FAPI_TRY(io::rmw(EDIP_TX_ZCAL_REQ, i_tgt, GRP3, LN0, 1));
 
-    // Delay before we start polling.  20ms was use from past p8 learning
-    FAPI_TRY(fapi2::delay(DLY_20MS, DLY_10MIL_CYCLES));
+
+fapi_try_exit:
+    FAPI_IMP("tx_zcal_run_sm: I/O EDI+ Dmi Exiting");
+    return fapi2::current_err;
+}
+
+/**
+ * @brief Tx Z Impedance Calibration State Machine
+ * @param[in] i_tgt FAPI2 Target
+ * @retval ReturnCode
+ */
+fapi2::ReturnCode tx_zcal_run_bus_poll(const DMI_TGT i_tgt)
+{
+    const uint64_t DLY_10US         = 10000;
+    const uint64_t DLY_1MIL_CYCLES  = 1000000;
+    const uint32_t TIMEOUT          = 200;
+    const uint8_t GRP3              = 3;
+    const uint8_t LN0               = 0;
+    uint32_t l_count                = 0;
+    uint64_t l_data                 = 0;
 
     // Poll Until Tx Impedance Calibration is done or errors out
     FAPI_TRY(io::read(EDIP_TX_IMPCAL_PB, i_tgt, GRP3, LN0, l_data));
@@ -725,7 +785,6 @@ fapi2::ReturnCode rx_dccal_poll_grp(const DMI_TGT i_tgt)
 {
     FAPI_IMP("rx_dccal_poll_grp: I/O EDI+ Dmi Entering");
     const uint8_t  TIMEOUT           = 200;
-    const uint64_t DLY_100MS         = 100000000;
     const uint64_t DLY_10MS          = 10000000;
     const uint64_t DLY_1MIL_CYCLES   = 1000000;
     const uint8_t  GRP3              = 3;
@@ -739,17 +798,17 @@ fapi2::ReturnCode rx_dccal_poll_grp(const DMI_TGT i_tgt)
     // In the pervasive unit model, this takes 750,000,000 sim cycles to finish
     //   on a group.  This equates to 30 loops with 25,000,000 delay each.
 
-    // Delay before we start polling.  100ms was use from past p8 learning
-    FAPI_TRY(fapi2::delay(DLY_100MS, DLY_1MIL_CYCLES),
-             "rx_dc_cal_poll: Fapi Delay Failed.");
-
     do
     {
         FAPI_DBG("I/O EDI+ Dmi Rx Dccal Polling Count(%d/%d).", l_poll_count, TIMEOUT);
 
-        FAPI_TRY(fapi2::delay(DLY_10MS, DLY_1MIL_CYCLES), "Fapi Delay Failed.");
-
         FAPI_TRY(io::read(EDIP_RX_DC_CALIBRATE_DONE, i_tgt, GRP3, LN0, l_data));
+
+        if (!io::get(EDIP_RX_DC_CALIBRATE_DONE, l_data))
+        {
+            FAPI_TRY(fapi2::delay(DLY_10MS, DLY_1MIL_CYCLES), "Fapi Delay Failed.");
+        }
+
     }
     while((++l_poll_count < TIMEOUT) && !io::get(EDIP_RX_DC_CALIBRATE_DONE, l_data));
 
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.H b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.H
index 6a662f6d8..d60b06dff 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.H
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_dccal.H
@@ -43,7 +43,7 @@
 #include <fapi2.H>
 
 typedef fapi2::Target<fapi2::TARGET_TYPE_DMI> DMI_TGT;
-typedef fapi2::ReturnCode (*p9_io_dmi_dccal_FP_t)(const DMI_TGT&);
+typedef fapi2::ReturnCode (*p9_io_dmi_dccal_FP_t)(fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
 
 extern "C"
 {
@@ -52,11 +52,11 @@ extern "C"
      * @brief A I/O EDI+ Procedure that runs Rx Dccal and Tx Z Impedance calibration
      * on every EDI+ DMI chiplet.
      *
-     * @param[in] i_tgt   Reference to DMI chiplet target
+     * @param[in] i_target_chip   Chip target
      *
      * @return FAPI2_RC_SUCCESS on success, error otherwise
      */
-    fapi2::ReturnCode p9_io_dmi_dccal(const DMI_TGT& i_tgt);
+    fapi2::ReturnCode p9_io_dmi_dccal(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
 
 } // extern "C"
 
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.C b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.C
index e4521c74f..ecce11e62 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.C
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.C
@@ -751,12 +751,11 @@ fapi_try_exit:
 /**
  * @brief A HWP that runs on every link of the DMI(EDI+)
  *
- * @param[in] i_mtgt   Reference to the Master Target
- * @param[in] i_stgt  Reference to the Slave Target
+ * @param[in] i_target_chip  Chip target
  *
  * @return FAPI2_RC_SUCCESS on success, error otherwise
  */
-fapi2::ReturnCode p9_io_dmi_linktrain(const DMI_TGT& i_mtgt, const CN_TGT& i_stgt)
+fapi2::ReturnCode p9_io_dmi_linktrain(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     FAPI_IMP("p9_io_dmi_linktrain: P9 I/O EDI+/EDI DMI Entering");
 
@@ -768,51 +767,95 @@ fapi2::ReturnCode p9_io_dmi_linktrain(const DMI_TGT& i_mtgt, const CN_TGT& i_stg
 
     char l_mtgt_str[fapi2::MAX_ECMD_STRING_LEN];
     char l_stgt_str[fapi2::MAX_ECMD_STRING_LEN];
-    fapi2::toString(i_mtgt, l_mtgt_str, fapi2::MAX_ECMD_STRING_LEN);
-    fapi2::toString(i_stgt, l_stgt_str, fapi2::MAX_ECMD_STRING_LEN);
 
-    FAPI_DBG("I/O DMI Targets: Target(%s) Connected(%s)", l_mtgt_str, l_stgt_str);
+    for (auto l_mtgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        //There should only be one centaur child
+        for (auto l_stgt : l_mtgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>())
+        {
+
+            fapi2::toString(l_mtgt, l_mtgt_str, fapi2::MAX_ECMD_STRING_LEN);
+            fapi2::toString(l_stgt, l_stgt_str, fapi2::MAX_ECMD_STRING_LEN);
+
+            FAPI_DBG("I/O DMI Targets: Target(%s) Connected(%s)", l_mtgt_str, l_stgt_str);
 
-    // Shorten timers if we are running in simulation
-    FAPI_TRY(p9_io_dmi_proc_shorten_timers(i_mtgt));
-    FAPI_TRY(p9_io_dmi_cn_shorten_timers(i_stgt));
+            // Shorten timers if we are running in simulation
+            FAPI_TRY(p9_io_dmi_proc_shorten_timers(l_mtgt));
+            FAPI_TRY(p9_io_dmi_cn_shorten_timers(l_stgt));
 
 
-    // Record the Bad Lane Vectors Prior to link training.
-    FAPI_TRY(get_dmi_proc_bad_lane_data(i_mtgt, l_m_pre_bad_data),
-             "Pre Training: Get Bad Lane Vector Failed on Master");
-    FAPI_TRY(get_dmi_cn_bad_lane_data(i_stgt, l_s_pre_bad_data),
-             "Pre Training: Get Bad Lane Vector Failed on Slave");
+            // Record the Bad Lane Vectors Prior to link training.
+            FAPI_TRY(get_dmi_proc_bad_lane_data(l_mtgt, l_m_pre_bad_data),
+                     "Pre Training: Get Bad Lane Vector Failed on Master");
+            FAPI_TRY(get_dmi_cn_bad_lane_data(l_stgt, l_s_pre_bad_data),
+                     "Pre Training: Get Bad Lane Vector Failed on Slave");
 
 
-    // Clock Serializer Init -- isn't strictly necessary but does line up the
-    //   clock serializer counter wit the data slices.
-    FAPI_TRY(tx_serializer_sync_power_on(i_mtgt), "tx_serializer_sync_power_on Failed.");
+            // Clock Serializer Init -- isn't strictly necessary but does line up the
+            //   clock serializer counter wit the data slices.
+            FAPI_TRY(tx_serializer_sync_power_on(l_mtgt), "tx_serializer_sync_power_on Failed.");
 
-    // TODO : For Centaur Only, Scan in pll settings with PFD360->1
+            // TODO : For Centaur Only, Scan in pll settings with PFD360->1
 
-    // Start Slave/Master Target Link Training
-    FAPI_TRY(linktrain_dmi_cn_start(i_stgt, State::WIRETEST), "P9 I/O DMI CN Start W Failed.");
-    FAPI_TRY(linktrain_dmi_proc_start(i_mtgt, State::WIRETEST), "P9 I/O DMI Proc Start W Failed.");
+            // Start Slave/Master Target Link Training
+            FAPI_TRY(linktrain_dmi_cn_start(l_stgt, State::WIRETEST), "P9 I/O DMI CN Start W Failed.");
+            FAPI_TRY(linktrain_dmi_proc_start(l_mtgt, State::WIRETEST), "P9 I/O DMI Proc Start W Failed.");
+        }
+    }
 
-    // Poll for Training to Complete on Master Target
-    FAPI_TRY(linktrain_poll(i_mtgt, i_stgt, State::WIRETEST), "P9 I/O DMI Proc Poll W Failed.");
+    for (auto l_mtgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        //There should only be one centaur child
+        for (auto l_stgt : l_mtgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>())
+        {
+            // Poll for Training to Complete on Master Target
+            FAPI_TRY(linktrain_poll(l_mtgt, l_stgt, State::WIRETEST), "P9 I/O DMI Proc Poll W Failed.");
+        }
+    }
 
     // TODO : For Centaur Only, Scan in pll settings with PFD360->0
+    for (auto l_mtgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        //There should only be one centaur child
+        for (auto l_stgt : l_mtgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>())
+        {
 
-    FAPI_TRY(linktrain_dmi_cn_start(i_stgt, State::DESKEW | State::EYEOPT), "P9 I/O DMI CN Start DERF Failed.");
-    FAPI_TRY(linktrain_dmi_proc_start(i_mtgt, State::DESKEW | State::EYEOPT), "P9 I/O DMI Proc Start DERF Failed.");
+            FAPI_TRY(linktrain_dmi_cn_start(l_stgt, State::DESKEW | State::EYEOPT), "P9 I/O DMI CN Start DERF Failed.");
+            FAPI_TRY(linktrain_dmi_proc_start(l_mtgt, State::DESKEW | State::EYEOPT), "P9 I/O DMI Proc Start DERF Failed.");
+        }
+    }
 
-    // Poll for Training to Complete on Master Target
-    FAPI_TRY(linktrain_poll(i_mtgt, i_stgt, State::DESKEW | State::EYEOPT), "P9 I/O DMI Proc Poll DERF Failed.");
+    for (auto l_mtgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        //There should only be one centaur child
+        for (auto l_stgt : l_mtgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>())
+        {
+            // Poll for Training to Complete on Master Target
+            FAPI_TRY(linktrain_poll(l_mtgt, l_stgt, State::DESKEW | State::EYEOPT), "P9 I/O DMI Proc Poll DERF Failed.");
+        }
+    }
 
     // DE / RF needs to split up due to HW220654
+    for (auto l_mtgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        //There should only be one centaur child
+        for (auto l_stgt : l_mtgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>())
+        {
 
-    FAPI_TRY(linktrain_dmi_cn_start(i_stgt, State::REPAIR | State::FUNCTIONAL), "P9 I/O DMI CN Start DERF Failed.");
-    FAPI_TRY(linktrain_dmi_proc_start(i_mtgt, State::REPAIR | State::FUNCTIONAL), "P9 I/O DMI Proc Start DERF Failed.");
+            FAPI_TRY(linktrain_dmi_cn_start(l_stgt, State::REPAIR | State::FUNCTIONAL), "P9 I/O DMI CN Start DERF Failed.");
+            FAPI_TRY(linktrain_dmi_proc_start(l_mtgt, State::REPAIR | State::FUNCTIONAL), "P9 I/O DMI Proc Start DERF Failed.");
+        }
+    }
 
-    // Poll for Training to Complete on Master Target
-    FAPI_TRY(linktrain_poll(i_mtgt, i_stgt, State::REPAIR | State::FUNCTIONAL), "P9 I/O DMI Proc Poll DERF Failed.");
+    for (auto l_mtgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        //There should only be one centaur child
+        for (auto l_stgt : l_mtgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>())
+        {
+            // Poll for Training to Complete on Master Target
+            FAPI_TRY(linktrain_poll(l_mtgt, l_stgt, State::REPAIR | State::FUNCTIONAL), "P9 I/O DMI Proc Poll DERF Failed.");
+        }
+    }
 
 
     // >> HW390103 -- Leave Tx Unload Clock Disable Off
@@ -820,21 +863,27 @@ fapi2::ReturnCode p9_io_dmi_linktrain(const DMI_TGT& i_mtgt, const CN_TGT& i_stg
     //FAPI_TRY(tx_serializer_sync_power_off(l_mtgt, l_stgt, GRP0),
     //          "tx_serializer_sync_power_off Failed.");
     // << HW390103 -- Leave Tx Unload Clock Disable Off
+    for (auto l_mtgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_DMI>())
+    {
+        //There should only be one centaur child
+        for (auto l_stgt : l_mtgt.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>())
+        {
 
-    // Record the Bad Lane Vectors after link training.
-    FAPI_TRY(get_dmi_proc_bad_lane_data(i_mtgt, l_m_post_bad_data),
-             "Post Training: Get Bad Lane Vector Failed on Master");
-    FAPI_TRY(get_dmi_cn_bad_lane_data(i_stgt, l_s_post_bad_data),
-             "Post Training: Get Bad Lane Vector Failed on Master");
-
+            // Record the Bad Lane Vectors after link training.
+            FAPI_TRY(get_dmi_proc_bad_lane_data(l_mtgt, l_m_post_bad_data),
+                     "Post Training: Get Bad Lane Vector Failed on Master");
+            FAPI_TRY(get_dmi_cn_bad_lane_data(l_stgt, l_s_post_bad_data),
+                     "Post Training: Get Bad Lane Vector Failed on Master");
 
-    // Check to see if the bad lanes match the bad lanes prior to link training.
-    //   If so, then that error has already been logged and we can clear the firs.
-    FAPI_TRY(check_dmi_proc_bad_lane_data(i_mtgt, l_m_pre_bad_data, l_m_post_bad_data),
-             "Post Training: Evaluate Firs Failed on Master");
-    FAPI_TRY(check_dmi_cn_bad_lane_data(i_stgt, l_s_pre_bad_data, l_s_post_bad_data),
-             "Post Training: Evaluate Firs Failed on Slave");
 
+            // Check to see if the bad lanes match the bad lanes prior to link training.
+            //   If so, then that error has already been logged and we can clear the firs.
+            FAPI_TRY(check_dmi_proc_bad_lane_data(l_mtgt, l_m_pre_bad_data, l_m_post_bad_data),
+                     "Post Training: Evaluate Firs Failed on Master");
+            FAPI_TRY(check_dmi_cn_bad_lane_data(l_stgt, l_s_pre_bad_data, l_s_post_bad_data),
+                     "Post Training: Evaluate Firs Failed on Slave");
+        }
+    }
 
 fapi_try_exit:
 
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.H b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.H
index b2ccd11ca..80c5082ac 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.H
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_dmi_linktrain.H
@@ -49,7 +49,7 @@
 typedef fapi2::Target<fapi2::TARGET_TYPE_DMI> DMI_TGT;
 typedef fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> CN_TGT;
 
-typedef fapi2::ReturnCode (*p9_io_dmi_linktrain_FP_t)(const DMI_TGT&, const CN_TGT&);
+typedef fapi2::ReturnCode (*p9_io_dmi_linktrain_FP_t)(fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
 
 extern "C"
 {
@@ -58,12 +58,11 @@ extern "C"
      * @brief A HWP that runs once on every link of the DMI(EDI+).
      *   The HWP will train both ends of the link.
      *
-     * @param[in] i_mtgt Reference to the Master Target
-     * @param[in] i_stgt Reference to the Slave Target
+     * @param[in] i_target_chip Chip target
      *
      * @return FAPI2_RC_SUCCESS on success, error otherwise
      */
-    fapi2::ReturnCode p9_io_dmi_linktrain(const DMI_TGT& i_mtgt, const CN_TGT& i_stgt);
+    fapi2::ReturnCode p9_io_dmi_linktrain(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
 
 } // extern "C"