apply HW423589 option1 (MCD disable) workaround for p9n DD2.1

Current FW uses option2 (alternate MCD configuration) to workaround
HW423589 for p9n DD2.1 hardware, which is desired for OP releases
supporting GPUs.

This commit adjusts the DD2.1 solution to option1 instead,
and can be cherry-picked into the enterprise release branches to
remove the per-socket memory resrictions which come as a side effect
of the current option2 setup.

Change-Id: I24ecf918a81964a3df6b1e3e18e60375d7646b45
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69718
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69847
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

5 files changed, 40 insertions, 40 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
index 2014227f2..29d6e2b1c 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
@@ -169,15 +169,15 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target<fapi2::TARGET_TYPE_CAPP>& TGT0
                 }
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_G_ON = 0x1;
                 l_scom_buffer.insert<4, 1, 63, uint64_t>(l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_G_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<3, 1, 63, uint64_t>(l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_VG_NOT_SYS_ON );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C
index 2728df278..da4f761cb 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C
@@ -126,15 +126,15 @@ fapi2::ReturnCode p9_int_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 l_scom_buffer.insert<49, 1, 63, uint64_t>(literal_0 );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_G_ON = 0x1;
                 l_scom_buffer.insert<47, 1, 63, uint64_t>(l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_G_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<46, 1, 63, uint64_t>(l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS_ON );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
index 30afa5a5e..c34baf8d3 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
@@ -124,29 +124,29 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 l_scom_buffer.insert<8, 3, 61, uint64_t>(literal_0x3 );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON = 0x1;
                 l_scom_buffer.insert<1, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON = 0x1;
                 l_scom_buffer.insert<5, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<2, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<6, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
index b08ba5471..e48166c54 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
@@ -677,57 +677,57 @@ fapi2::ReturnCode p9_nx_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 }
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON = 0x1;
                 l_scom_buffer.insert<1, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON = 0x1;
                 l_scom_buffer.insert<5, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_GROUP_ON = 0x1;
                 l_scom_buffer.insert<9, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_GROUP_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_GROUP_ON = 0x1;
                 l_scom_buffer.insert<13, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_GROUP_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<2, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<6, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<10, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_VG_NOT_SYS_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_VG_NOT_SYS_ON = 0x1;
                 l_scom_buffer.insert<14, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_VG_NOT_SYS_ON );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C
index 3803c89ed..44cd049f9 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C
@@ -168,29 +168,29 @@ fapi2::ReturnCode p9_vas_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             l_scom_buffer.insert<20, 8, 56, uint64_t>(literal_0xFC );
             l_scom_buffer.insert<28, 8, 56, uint64_t>(literal_0xFC );
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_WR_ON = 0x1;
                 l_scom_buffer.insert<1, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_WR_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_RD_ON = 0x1;
                 l_scom_buffer.insert<5, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_RD_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_WR_ON = 0x1;
                 l_scom_buffer.insert<2, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_WR_ON );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x23)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
             {
                 constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_RD_ON = 0x1;
                 l_scom_buffer.insert<6, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_RD_ON );