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| author | Jenny Huynh <jhuynh@us.ibm.com> | 2018-08-29 17:04:51 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-09-14 16:39:54 -0500 |
| commit | 25be20644f96cfdea7edd265b1fbd4525bfea9d4 (patch) | |
| tree | 5b9bc6e01b9ad5c60de7aa3adff3f4d2b6106885 /src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C | |
| parent | 076c45f663b8fe786b9006b2ec575639012bf807 (diff) | |
| download | talos-hostboot-25be20644f96cfdea7edd265b1fbd4525bfea9d4.tar.gz talos-hostboot-25be20644f96cfdea7edd265b1fbd4525bfea9d4.zip | |
SW427193 / HW461448: Enable memory controller wat
Change-Id: I2fc4cf0dda43d4eba543024605c8f358e22e1bae
CQ:SW427193
CQ:HW461448
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65476
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Adam S. Hale <adam.samuel.hale@ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65510
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C index 8b526c36e..977fe9103 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C @@ -47,6 +47,8 @@ constexpr uint64_t literal_0b0000000000001000 = 0b0000000000001000; constexpr uint64_t literal_0b10 = 0b10; constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_5 = 5; +constexpr uint64_t literal_0xE = 0xE; +constexpr uint64_t literal_0b100 = 0b100; fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2) @@ -346,6 +348,13 @@ fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0, FAPI_TRY(fapi2::putScom(TGT0, 0x501081bull, l_scom_buffer)); } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x501081cull, l_scom_buffer )); + + l_scom_buffer.insert<32, 4, 60, uint64_t>(literal_0xE ); + l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_0b100 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x501081cull, l_scom_buffer)); + } }; fapi_try_exit: |
