CORE/CACHE: core/cache/l2_stopclocks Level 2

Change-Id: Iba5a4402d748b9f470243e92c3f712a4aa9dc4e9
Original-Change-Id: Ie4bce2bcaf0ffb2d1e57370312c4536356b62efc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27338
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36109
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

2 files changed, 132 insertions, 10 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
index c17a10e2d..2a2d7b3ae 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
@@ -32,7 +32,7 @@
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
 // *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
 // *HWP Team               : PM
-// *HWP Consumed by        : HB:PREV
+// *HWP Consumed by        : HB:PERV
 // *HWP Level              : 2
 
 //------------------------------------------------------------------------------
@@ -48,17 +48,137 @@
 // Constant Definitions
 //------------------------------------------------------------------------------
 
+enum P9_HCD_L2_STOPCLOCKS_CONSTANTS
+{
+    L2_CLK_SYNC_TIMEOUT_IN_MS = 1,
+    L2_CLK_STOP_TIMEOUT_IN_MS = 1
+};
+
 //------------------------------------------------------------------------------
 // Procedure: Quad Clock Stop
 //------------------------------------------------------------------------------
 
 fapi2::ReturnCode
 p9_hcd_l2_stopclocks(
-    const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target)
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+    const p9hcd::P9_HCD_EX_CTRL_CONSTANTS       i_select_ex)
 {
-    FAPI_INF(">>p9_hcd_l2_stopclocks");
+    FAPI_INF(">>p9_hcd_l2_stopclocks: ex[%d]",  i_select_ex);
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint32_t                                    l_timeout;
+    uint64_t                                    l_region_clock = 0;
+    uint64_t                                    l_l2sync_clock = 0;
+    uint64_t                                    l_l2mask_pscom = 0;
+    uint8_t                                     l_attr_chip_unit_pos = 0;
+    auto l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    auto l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET;
+
+    if (i_select_ex & p9hcd::EVEN_EX)
+    {
+        l_region_clock |= p9hcd::CLK_REGION_EX0_L2;
+        l_l2sync_clock |= BIT64(36);
+        l_l2mask_pscom |= BIT64(2) | BIT64(10);
+    }
+
+    if (i_select_ex & p9hcd::ODD_EX)
+    {
+        l_region_clock |= p9hcd::CLK_REGION_EX1_L2;
+        l_l2sync_clock |= BIT64(37);
+        l_l2mask_pscom |= BIT64(3) | BIT64(11);
+    }
+
+    // -------------------------
+    // Prepare to stop L2 clocks
+    // -------------------------
+
+    FAPI_DBG("Assert L2 pscom masks via RING_FENCE_MASK_LATCH_REG[2/3,10/11]");
+    FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l2mask_pscom));
+
+    // -------------------------------
+    // Stop L2 clocks
+    // -------------------------------
+
+    FAPI_DBG("Clear all SCAN_REGION_TYPE bits");
+    FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
+
+    FAPI_DBG("Stop L2 clocks via CLK_REGION");
+    l_data64 = (p9hcd::CLK_STOP_CMD           |
+                l_region_clock                |
+                p9hcd::CLK_THOLD_ALL);
+    FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
+
+    FAPI_DBG("Poll for L2 clocks stopped via CPLT_STAT0[8]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                L2_CLK_STOP_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
+    }
+    while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_L2CLKSTOP_TIMEOUT()
+                .set_EQ_TARGET(i_target)
+                .set_EQCPLTSTAT(l_data64),
+                "L2 Clock Stop Timeout");
+
+    FAPI_DBG("Check L2 clocks stopped");
+    FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
+
+    FAPI_ASSERT((((~l_data64) & l_region_clock) == 0),
+                fapi2::PMPROC_L2CLKSTOP_FAILED()
+                .set_EQ_TARGET(i_target)
+                .set_EQCLKSTAT(l_data64),
+                "L2 Clock Stop Failed");
+    FAPI_DBG("L2 clocks stopped now");
+
+    // -------------------------------
+    // Disable L2 clock sync
+    // -------------------------------
+
+    FAPI_DBG("Drop L2 clock sync enables via QPPM_EXCGCR[36,37]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_CLEAR, l_l2sync_clock));
+
+    FAPI_DBG("Poll for L2 clock sync dones to drop via QPPM_QACSR[36,37]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                L2_CLK_SYNC_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_QPPM_QACSR, l_data64));
+    }
+    while(((l_data64 & l_l2sync_clock)) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_CACHECLKSYNCDROP_TIMEOUT().set_EQPPMQACSR(l_data64),
+                "L2 Clock Sync Drop Timeout");
+    FAPI_DBG("L2 clock sync dones dropped");
+
+    // -------------------------------
+    // Fence up
+    // -------------------------------
+
+    FAPI_DBG("Assert regional fences via CPLT_CTRL1[8/9]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, l_region_clock));
+
+
+    // -------------------------------
+    // Update QSSR
+    // -------------------------------
+
+    FAPI_DBG("Set EX as stopped in QSSR");
+    FAPI_TRY(putScom(l_chip, PU_OCB_OCI_QSSR_OR,
+                     ((uint64_t)i_select_ex << SHIFT64((l_attr_chip_unit_pos << 1) + 1))));
+
+
+fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_l2_stopclocks");
-    return fapi2::FAPI2_RC_SUCCESS;
+    return fapi2::current_err;
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H
index 8ae5b3c3b..ef3e95a15 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H
@@ -31,18 +31,19 @@
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
 // *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
 // *HWP Team               : PM
-// *HWP Consumed by        : HB:PREV
+// *HWP Consumed by        : HB:PERV
 // *HWP Level              : 2
 
-#ifndef __P9_HCD_CACHE_STOPCLOCKS_H__
-#define __P9_HCD_CACHE_STOPCLOCKS_H__
+#ifndef __P9_HCD_L2_STOPCLOCKS_H__
+#define __P9_HCD_L2_STOPCLOCKS_H__
 
 #include <fapi2.H>
 
 /// @typedef p9_hcd_l2_stopclocks_FP_t
 /// function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_hcd_l2_stopclocks_FP_t) (
-    const fapi2::Target<fapi2::TARGET_TYPE_EX>&);
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&,
+    const p9hcd::P9_HCD_EX_CTRL_CONSTANTS);
 
 extern "C"
 {
@@ -52,8 +53,9 @@ extern "C"
 /// @return FAPI2_RC_SUCCESS if success, else error code
     fapi2::ReturnCode
     p9_hcd_l2_stopclocks(
-        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target);
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+        const p9hcd::P9_HCD_EX_CTRL_CONSTANTS       i_select_ex);
 
 }
 
-#endif  // __P9_HCD_CACHE_STOPCLOCKS_H__
+#endif  // __P9_HCD_L2_STOPCLOCKS_H__