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| author | Prasad Bg Ranganath <prasadbgr@in.ibm.com> | 2018-08-28 07:09:48 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-09-04 10:45:59 -0500 |
| commit | ae850cf7588d14c4456991d5548cc4537bcd7964 (patch) | |
| tree | a0611580dd6502b33e5cbf21fb18b7fba5c49173 /src/import/chips/p9/procedures/hwp/cache | |
| parent | 84923368d03fcf5a7bd09f9a6aa1dc692d65db3e (diff) | |
| download | talos-hostboot-ae850cf7588d14c4456991d5548cc4537bcd7964.tar.gz talos-hostboot-ae850cf7588d14c4456991d5548cc4537bcd7964.zip | |
PM:Some more cleanups in update_ec_eq procedure for core unit xstop case
- Enabled EX check. even if it's EQ is functional
- one more check of clock power off which is
required for mpipl case.
- had one bug during l2/l3 stop clock which fixes status bit update.
Actually clock was stopped but the status bit was not set
in EQ_CLOCK_STAT register.
Key_Cronus_Test=PM_REGRESS
Change-Id: I7e8dbea00235ade5a692198dde7c2e6758809b9f
CQ:SW443537
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65360
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65365
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/cache')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C index 4c92740e2..1fed720f6 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C @@ -101,6 +101,15 @@ p9_hcd_cache_stopclocks( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, l_sys, l_is_mpipl)); + //Check if EQ is powered off; if so, return + FAPI_TRY(fapi2::getScom(i_target, EQ_PPM_PFSNS, l_data64), + "Error reading data from EQ_PPM_PFSNS"); + + if (l_data64.getBit<EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE>()) + { + return fapi2::current_err; + } + if(l_is_mpipl) { // PB_PURGE related SCOMs should be added to the beginning of |
