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| author | Jenny Huynh <jhuynh@us.ibm.com> | 2018-03-05 11:27:23 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-07 21:42:15 -0500 |
| commit | 3d8051b7b2e7f053b36dc6db8028094aaee53f39 (patch) | |
| tree | ef4ca9f50c55d087d06c43d81d1b6e13a190c08d /src/import/chips/p9/procedures/hwp/cache | |
| parent | e80082e3a96a6be52aafa59e9f3aeb11ee51589f (diff) | |
| download | talos-hostboot-3d8051b7b2e7f053b36dc6db8028094aaee53f39.tar.gz talos-hostboot-3d8051b7b2e7f053b36dc6db8028094aaee53f39.zip | |
Reset L3 error status register for next CE/UE capture
Change-Id: I92320a6bc869b9cd1df05483f2d58afdb0bfad13
CQ:SW419528
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55041
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55051
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/cache')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_l3err_extract.C | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_l3err_extract.C b/src/import/chips/p9/procedures/hwp/cache/p9_l3err_extract.C index f245c3166..d2d1d92a4 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_l3err_extract.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_l3err_extract.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -355,6 +355,13 @@ fapi2::ReturnCode p9_l3err_extract( o_err_data.hashed_real_address_45_56 = real_address45_56; o_err_data.cache_read_address = err_stat_ra; + // Reset error status register for next capture + FAPI_DBG("Clearing error status register for next capture"); + + FAPI_TRY(fapi2::putScom(i_target, EX_ED_RD_ERR_STAT_REG0, 0x0000000000000000), + "Error from clearing L3 error status register (L3_eDRAM_RD_ERR_STAT_Register_0)"); + + fapi_try_exit: // mark HWP exit FAPI_DBG("Exiting ..."); |
