L3 Update - p9_hcd_cache_stopclocks HWP

Change-Id: Id2d05ebed42c6456557f88917e1b8f9c1a8daf00
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45735
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45744
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 46 insertions, 38 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
index 7fcc8719d..d126020a6 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
@@ -30,26 +30,25 @@
 
 // *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
-// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP FW Owner           : Amit Tendolkar <amit.tendolkar@in.ibm.com>
 // *HWP Team               : PM
 // *HWP Consumed by        : HB:PERV
-// *HWP Level              : 2
+// *HWP Level              : 3
 
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
-
 #include <p9_misc_scom_addresses.H>
 #include <p9_quad_scom_addresses.H>
 #include <p9_hcd_common.H>
 #include <p9_common_clk_ctrl_state.H>
-#include "p9_hcd_l2_stopclocks.H"
-#include "p9_hcd_cache_stopclocks.H"
+#include <p9_hcd_l2_stopclocks.H>
+#include <p9_hcd_cache_stopclocks.H>
+#include <p9_quad_scom_addresses_fld.H>
 
 //------------------------------------------------------------------------------
 // Constant Definitions
 //------------------------------------------------------------------------------
-
 enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS
 {
     CACHE_CLK_STOP_POLLING_HW_NS_DELAY     = 10000,
@@ -62,7 +61,7 @@ enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS
 //------------------------------------------------------------------------------
 // Procedure: Quad Clock Stop
 //------------------------------------------------------------------------------
-
+// See doxygen in header file
 fapi2::ReturnCode
 p9_hcd_cache_stopclocks(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
@@ -99,7 +98,7 @@ p9_hcd_cache_stopclocks(
         // region including PBIEQ clock domain is being stopped, which
         // incidentally should always be the case for MPIPL
         l_data64.flush<0>();
-        l_data64.setBit<30>();
+        l_data64.setBit<EQ_QPPM_QCCR_PB_PURGE_REQ>();
         // Set bit 30 in EQ_QPPM_QCCR_SCOM2(100F01BF) Reg, Pulse to the
         // Powerbus logic in the Cache clock domain to request them to purge
         // their async buffers in preparation to power off the Quad
@@ -113,9 +112,8 @@ p9_hcd_cache_stopclocks(
             // Acknowledgement from Powerbus that the buffers are empty
             // and can safely be fenced & clocked off.
             FAPI_TRY(fapi2::getScom(i_target, EQ_QPPM_QCCR_SCOM, l_data64));
-            bool l_poll_data = l_data64.getBit<31>();
 
-            if(l_poll_data == 1)
+            if(l_data64.getBit<EQ_QPPM_QCCR_PB_PURGE_DONE_LVL>())
             {
                 break;
             }
@@ -131,10 +129,11 @@ p9_hcd_cache_stopclocks(
                     fapi2::QPPM_QCCR_PB_PURGE_DONE_LVL_TIMEOUT()
                     .set_TARGET(i_target)
                     .set_EQPPMQCCR(l_data64),
-                    "QPPM_QCCR_PB_PURGE_DONE_LVL Reg bit 31 not set.");
+                    "QPPM_QCCR_PB_PURGE_DONE_LVL Reg bit _QPPM_QCCR_PB_PURGE_DONE_LVL not set.");
 
+        // Clear purge request
         l_data64.flush<0>();
-        l_data64.setBit<30>();
+        l_data64.setBit<EQ_QPPM_QCCR_PB_PURGE_REQ>();
         FAPI_TRY(fapi2::putScom(i_target, EQ_QPPM_QCCR_SCOM1, l_data64));
     }
 
@@ -142,7 +141,7 @@ p9_hcd_cache_stopclocks(
                            l_attr_vdm_enabled));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
                            l_attr_chip_unit_pos));
-//  l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET;
+    //  l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET;
     l_attr_chip_unit_pos = l_attr_chip_unit_pos - 0x10;
 
     if (i_select_regions & p9hcd::CLK_REGION_EX0_L3)
@@ -161,10 +160,9 @@ p9_hcd_cache_stopclocks(
     FAPI_DBG("Check PM_RESET_STATE_INDICATOR via GPMMR[15]");
     FAPI_TRY(getScom(i_target, EQ_PPM_GPMMR_SCOM, l_data64));
 
-    if (!l_data64.getBit<15>())
+    if (!l_data64.getBit<EQ_PPM_GPMMR_RESET_STATE_INDICATOR>())
     {
         FAPI_DBG("Gracefully turn off power management, if fail, continue anyways");
-        /// @todo RTC158181 suspend_pm()
     }
 
     FAPI_DBG("Check cache clock controller status");
@@ -182,15 +180,15 @@ p9_hcd_cache_stopclocks(
     FAPI_DBG("Check PERV fence status for access to CME via CPLT_CTRL1[4]");
     FAPI_TRY(getScom(i_target, EQ_CPLT_CTRL1, l_temp64));
 
-    if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0)
+    if (l_data64.getBit<EQ_CLOCK_STAT_SL_STATUS_PERV>() == 0 &&
+        l_temp64.getBit<EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE>() == 0)
     {
-        /// @todo RTC158181 disable l2 snoop? disable lco? assert refresh quiesce?
         FAPI_DBG("Assert L3 pscom masks via RING_FENCE_MASK_LATCH_REG[4-9]");
         FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l3mask_pscom));
     }
 
     FAPI_DBG("Assert chiplet fence via NET_CTRL0[18]");
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(18)));
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(EQ_NET_CTRL0_FENCE_EN)));
 
     // -------------------------------
     // Stop L2 clocks
@@ -247,17 +245,21 @@ p9_hcd_cache_stopclocks(
 
         FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
     }
-    while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0));
+    while((!l_data64.getBit<EQ_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>()) && ((--l_loops1ms) != 0));
 
     FAPI_ASSERT((l_loops1ms != 0),
-                fapi2::PMPROC_CACHECLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64),
+                fapi2::PMPROC_CACHECLKSTOP_TIMEOUT()
+                .set_TARGET(i_target)
+                .set_EQCPLTSTAT(l_data64),
                 "Cache Clock Stop Timeout");
 
     FAPI_DBG("Check cache clocks stopped");
     FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
 
     FAPI_ASSERT((((~l_data64) & l_region_clock) == 0),
-                fapi2::PMPROC_CACHECLKSTOP_FAILED().set_EQCLKSTAT(l_data64),
+                fapi2::PMPROC_CACHECLKSTOP_FAILED()
+                .set_TARGET(i_target)
+                .set_EQCLKSTAT(l_data64),
                 "Cache Clock Stop Failed");
     FAPI_DBG("Cache clocks stopped now");
 
@@ -266,7 +268,7 @@ p9_hcd_cache_stopclocks(
     // -------------------------------
 
     FAPI_DBG("Assert vital fence via CPLT_CTRL1[3]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3)));
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(EQ_CPLT_CTRL1_TC_VITL_REGION_FENCE)));
 
     l_region_fence = l_region_clock;
 
@@ -356,4 +358,3 @@ fapi_try_exit:
     FAPI_INF("<<p9_hcd_cache_stopclocks");
     return fapi2::current_err;
 }
-
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H
index a093cbcea..65012af02 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H
@@ -29,10 +29,10 @@
 
 // *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
-// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP FW Owner           : Amit Tendolkar <amit.tendolkar@in.ibm.com>
 // *HWP Team               : PM
 // *HWP Consumed by        : HB:PERV
-// *HWP Level              : 2
+// *HWP Level              : 3
 
 #ifndef __P9_HCD_CACHE_STOPCLOCKS_H__
 #define __P9_HCD_CACHE_STOPCLOCKS_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
index 73d4227c4..943838065 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
@@ -30,10 +30,10 @@
 
 // *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
-// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP FW Owner           : Amit Tendolkar <amit.tendolkar@in.ibm.com>
 // *HWP Team               : PM
 // *HWP Consumed by        : HB:PERV
-// *HWP Level              : 2
+// *HWP Level              : 3
 
 //------------------------------------------------------------------------------
 // Includes
@@ -43,7 +43,8 @@
 #include <p9_quad_scom_addresses.H>
 #include <p9_hcd_common.H>
 #include <p9_common_clk_ctrl_state.H>
-#include "p9_hcd_l2_stopclocks.H"
+#include <p9_hcd_l2_stopclocks.H>
+#include <p9_quad_scom_addresses_fld.H>
 
 //------------------------------------------------------------------------------
 // Constant Definitions
@@ -104,7 +105,7 @@ p9_hcd_l2_stopclocks(
     FAPI_DBG("Check PM_RESET_STATE_INDICATOR via GPMMR[15]");
     FAPI_TRY(getScom(i_target, EQ_PPM_GPMMR_SCOM, l_data64));
 
-    if (!l_data64.getBit<15>())
+    if (!l_data64.getBit<EQ_PPM_GPMMR_RESET_STATE_INDICATOR>())
     {
         FAPI_DBG("Gracefully turn off power management, if fail, continue anyways");
         /// @todo RTC158181 suspend_pm()
@@ -125,7 +126,8 @@ p9_hcd_l2_stopclocks(
     FAPI_DBG("Check PERV fence status for access to CME via CPLT_CTRL1[4]");
     FAPI_TRY(getScom(i_target, EQ_CPLT_CTRL1, l_temp64));
 
-    if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0)
+    if (!l_data64.getBit<EQ_CLOCK_STAT_SL_STATUS_PERV>() &&
+        !l_temp64.getBit<EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE>())
     {
         FAPI_DBG("Assert L2 pscom masks via RING_FENCE_MASK_LATCH_REG[2/3,10/11]");
         FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l2mask_pscom));
@@ -154,17 +156,22 @@ p9_hcd_l2_stopclocks(
 
         FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
     }
-    while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0));
+    while((!l_data64.getBit<EQ_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>()) &&
+          ((--l_loops1ms) != 0));
 
     FAPI_ASSERT((l_loops1ms != 0),
-                fapi2::PMPROC_L2CLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64),
+                fapi2::PMPROC_L2CLKSTOP_TIMEOUT()
+                .set_TARGET(i_target)
+                .set_EQCPLTSTAT(l_data64),
                 "L2 Clock Stop Timeout");
 
     FAPI_DBG("Check L2 clocks stopped");
     FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
 
     FAPI_ASSERT((((~l_data64) & l_region_clock) == 0),
-                fapi2::PMPROC_L2CLKSTOP_FAILED().set_EQCLKSTAT(l_data64),
+                fapi2::PMPROC_L2CLKSTOP_FAILED()
+                .set_TARGET(i_target)
+                .set_EQCLKSTAT(l_data64),
                 "L2 Clock Stop Failed");
     FAPI_DBG("L2 clocks stopped now");
 
@@ -188,7 +195,9 @@ p9_hcd_l2_stopclocks(
     while(((l_data64 & l_l2sync_clock)) && ((--l_loops1ms) != 0));
 
     FAPI_ASSERT((l_loops1ms != 0),
-                fapi2::PMPROC_CACHECLKSYNCDROP_TIMEOUT().set_EQPPMQACSR(l_data64),
+                fapi2::PMPROC_L2CLKSYNCDROP_TIMEOUT()
+                .set_TARGET(i_target)
+                .set_EQPPMQACSR(l_data64),
                 "L2 Clock Sync Drop Timeout");
     FAPI_DBG("L2 clock sync dones dropped");
 
@@ -212,4 +221,3 @@ fapi_try_exit:
     FAPI_INF("<<p9_hcd_l2_stopclocks");
     return fapi2::current_err;
 }
-
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H
index ef3e95a15..14bf00982 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H
@@ -29,10 +29,9 @@
 
 // *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
-// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP FW Owner           : Amit Tendolkar <amit.tendolkar@in.ibm.com>
 // *HWP Team               : PM
 // *HWP Consumed by        : HB:PERV
-// *HWP Level              : 2
 
 #ifndef __P9_HCD_L2_STOPCLOCKS_H__
 #define __P9_HCD_L2_STOPCLOCKS_H__
@@ -49,7 +48,7 @@ extern "C"
 {
 
 /// @brief Quad Clock Stop
-/// @param [in] i_target TARGET_TYPE_EQ target
+/// @param[in]   i_target TARGET_TYPE_EQ target
 /// @return FAPI2_RC_SUCCESS if success, else error code
     fapi2::ReturnCode
     p9_hcd_l2_stopclocks(