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| author | Shelton Leung <sleung@us.ibm.com> | 2016-09-29 13:58:10 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-10-07 00:41:57 -0400 |
| commit | ee5228736e77fe2c245d5aead800cf7e26b46c09 (patch) | |
| tree | fe3be95ec5240750e4fd46cb20e008435dc826e4 /src/import/chips/p9/initfiles | |
| parent | d713902adb779457f39d5af7d881a7ae383e338c (diff) | |
| download | talos-hostboot-ee5228736e77fe2c245d5aead800cf7e26b46c09.tar.gz talos-hostboot-ee5228736e77fe2c245d5aead800cf7e26b46c09.zip | |
MCA initfile added support for CL != TRP != TRCD, ODT, CID
Remove extra whitespace
Change-Id: Ie6fcca62595c5a14ce20c051a4bb9357c80bd794
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30438
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30445
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/initfiles')
| -rw-r--r-- | src/import/chips/p9/initfiles/p9.mca.scom.initfile | 155 |
1 files changed, 155 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile index 3b2ec7707..47cd87692 100644 --- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile @@ -118,6 +118,11 @@ define def_REFRESH_INTERVAL = ((MCS.ATTR_EFF_DRAM_TREFI[def_PORT_INDEX])/( define def_RANK_SWITCH_TCK = 4 + ((MCBIST.ATTR_MSS_FREQ-1866)/267); # 1866: 4 2133: 5 2400: 6 2667: 7 define def_BUS_TURNAROUND_TCK = 4 + ((MCBIST.ATTR_MSS_FREQ-1866)/267); # 1866: 4 2133: 5 2400: 6 2667: 7 +define def_SLOT0_DRAM_STACK_HEIGHT = ( MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][0] + / MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0] ); +define def_SLOT1_DRAM_STACK_HEIGHT = ( MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][1] + / MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][1] ); + #--****************************************************************************** #-- Dial Assignments #--****************************************************************************** @@ -432,6 +437,156 @@ ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TXSDLL [when=S] { 939, (def_MSS_FREQ_EQ_2667==1); } +# CID +# Slot 0 +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S0_CID [when=S] { + spyv; + 0b000; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S1_CID [when=S] { + spyv; + 0b100; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S2_CID [when=S] { + spyv; + 0b010; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S3_CID [when=S] { + spyv; + 0b110; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S4_CID [when=S] { + spyv, expr; + 0b001, (def_SLOT0_DRAM_STACK_HEIGHT == 8); + 0b000, (def_SLOT0_DRAM_STACK_HEIGHT != 8); +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S5_CID [when=S] { + spyv, expr; + 0b101, (def_SLOT0_DRAM_STACK_HEIGHT == 8); + 0b100, (def_SLOT0_DRAM_STACK_HEIGHT != 8); +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S6_CID [when=S] { + spyv, expr; + 0b011, (def_SLOT0_DRAM_STACK_HEIGHT == 8); + 0b010, (def_SLOT0_DRAM_STACK_HEIGHT != 8); +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S7_CID [when=S] { + spyv, expr; + 0b111, (def_SLOT0_DRAM_STACK_HEIGHT == 8); + 0b110, (def_SLOT0_DRAM_STACK_HEIGHT != 8); +} +# Slot 1 +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S0_CID [when=S] { + spyv; + 0b000; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S1_CID [when=S] { + spyv; + 0b100; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S2_CID [when=S] { + spyv; + 0b010; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S3_CID [when=S] { + spyv; + 0b110; +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S4_CID [when=S] { + spyv, expr; + 0b001, (def_SLOT1_DRAM_STACK_HEIGHT == 8); + 0b000, (def_SLOT1_DRAM_STACK_HEIGHT != 8); +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S5_CID [when=S] { + spyv, expr; + 0b101, (def_SLOT1_DRAM_STACK_HEIGHT == 8); + 0b100, (def_SLOT1_DRAM_STACK_HEIGHT != 8); +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S6_CID [when=S] { + spyv, expr; + 0b011, (def_SLOT1_DRAM_STACK_HEIGHT == 8); + 0b010, (def_SLOT1_DRAM_STACK_HEIGHT != 8); +} +ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S7_CID [when=S] { + spyv, expr; + 0b111, (def_SLOT1_DRAM_STACK_HEIGHT == 8); + 0b110, (def_SLOT1_DRAM_STACK_HEIGHT != 8); +} + +# ODT RD +# Slot 0 +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK0_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][0]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK1_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][1]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK2_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][2]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK3_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][3]; +} +# Slot 1 +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK4_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][0]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK5_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][1]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK6_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][2]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK7_RD_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][3]; +} + +# ODT WR +# Slot 0 +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK0_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][0]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK1_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][1]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK2_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][2]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK3_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][3]; +} +# Slot 1 +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK4_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][0]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK5_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][1]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK6_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][2]; +} +ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK7_WR_ODT [when=S] { + spyv; + MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][3]; +} + + + #################################################### # DD1 WORKAROUNDS |
