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| author | Shelton Leung <sleung@us.ibm.com> | 2017-07-22 10:43:40 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-07-26 10:34:48 -0400 |
| commit | e0e8a621a681d98d3ad0a3fb0a03abc203d3ca03 (patch) | |
| tree | 9445b46d26b669a8ee573a6c8b5715c34596282d /src/import/chips/p9/initfiles | |
| parent | fd029f5afa54473a055a9b938d53da2e556b5a75 (diff) | |
| download | talos-hostboot-e0e8a621a681d98d3ad0a3fb0a03abc203d3ca03.tar.gz talos-hostboot-e0e8a621a681d98d3ad0a3fb0a03abc203d3ca03.zip | |
rdtag_dly +1 for 2666 for better memory corners
Change-Id: I13186fb7099cd63c621d530685139fb0b59eccda
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43461
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: KEVIN MCILVAIN <kmcilva@us.ibm.com>
Dev-Ready: KEVIN MCILVAIN <kmcilva@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANUWAT SAETOW <asaetow@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43462
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/initfiles')
| -rw-r--r-- | src/import/chips/p9/initfiles/p9n.mca.scom.initfile | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/src/import/chips/p9/initfiles/p9n.mca.scom.initfile b/src/import/chips/p9/initfiles/p9n.mca.scom.initfile index e12ea9ceb..1363917e2 100644 --- a/src/import/chips/p9/initfiles/p9n.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9n.mca.scom.initfile @@ -286,23 +286,27 @@ ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY [when=S] { ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RDTAG_DLY [when=S] { # ATTR_EFF_DIMM_TYPE: CDIMM = 0 RDIMM = 1 UDIMM = 2 LRDIMM = 3 spyv, expr; - # rdtag_dly + 3 + rdptrdly > PHY DELAY + CL - # rdtag_dly > PHY DELAY + CL - 3 - rdptrdly - # PHY DELAY = 12 for 1866 and 2133, 13 for 2400 and 2666, +1 for LRDIMM - # rdptrdly = 1 - # 4/20/2017 during performance test, experimentally found can run at -1 value + # 1/17/2017 INITIAL CONCEPT (HAS SINCE BEEN ADJUSTED): + # rdtag_dly + 3 + rdptrdly > PHY DELAY + CL + # rdtag_dly > PHY DELAY + CL - 3 - rdptrdly + # PHY DELAY = 12 for 1866 and 2133, 13 for 2400 and 2666, +1 for LRDIMM + # rdptrdly = 1 + # 4/20/2017 ADJUST #1: during performance test, experimentally found can run at -1 value + # 7/24/2017 ADJUST #2: +1 on 2666, to address fails discovered at 2666 by memory team + # + # RESULTANT BELOW: 17, def_IS_SIM; 7 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM 7 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM - 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM + 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM - 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM + 10 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM } |
