Change MCA initfile to encorporate VBU inits

  Update VBU, other attribute files

Change-Id: I338a038711f872850a00507116d30f2027ac6d5c
Original-Change-Id: I7d4aece1e5cea96791a2a9abecfbef2218b728da
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24168
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26543
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 408 insertions, 7 deletions

diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
index 99f8f5be2..ef5392325 100644
--- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile
+++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
@@ -1,3 +1,59 @@
+#  Joe's initfile reference page:
+#  https://w3-connections.ibm.com/wikis/home?lang=en-us#!/wiki/W9dc674bd1c19_432e_9f66_0e8b6ce7195f/page/P9%20Initfile%20Strategy%20%26%20Execution
+#  http://ausxgsatm2.austin.ibm.com/gsa/home/j/m/jmcgill/web/public/p8/initfiles/mba_def.initfile
+
+#--******************************************************************************
+#-- ISSUES TO RESOVLE
+#--******************************************************************************
+# ANDRE missing attributes
+#      ATTR_EFF_TCCD_S disappeared (temp commented to 4 for now)
+#--******************************************************************************
+#-- IMPORTANT SUPPORT NOTES AS OF 4/21/2016
+#--******************************************************************************
+# Currently only supports DIMMS where CL=TRCD=TRP (ie 16-16-16)
+#      Steve Powell says he's seen DIMMs that don't match
+#      What needs to be done to support other DIMMs
+#           Replace def_MEM_TYPE_1866_13_13_13 variables with freq+CL variables 
+#                Because TRCD and TRP don't really matter for the equations that this variable is being used for
+#                So we should rewrite these equations in terms of just freq+CL
+# Here we assume WL = ATTR_EFF_DRAM_CWL (which is true if no Additive Latency / Posted CAS). 
+#      So no support for Posted CAS / Additive latency
+# Only supports Burst Length 8 (CODE AND LOGIC STATEMENT)
+#      Initfile is hardcoded assuming BL=8 and BL/2=4
+#      Attribute does exist for Burst length. However, Nimbus logic does NOT support any other burst lengths
+#           If other burst lengths are to be supported, a logic change would be required
+# Only supports RDIMM with RDIMM and LRDIMM with LRDIMM, no mixing (CODE AND LOGIC STATEMENT)
+#      Logic would have to support different wr data delays to differen DIMMs. It does NOT.
+# Enhancements to be done later: ATTR_EFF_RDTAG_DLY and ATTR_EFF_WRDATA_DLY attributes
+#      What needs to be done to support other DIMMs
+#           ATTR_EFF_RDTAG_DLY and ATTR_EFF_WRDATA_DLY attributes (better to calculate in code than init file)
+#           MBA_DSM0Q_CFG_RDTAG_DLY to use ATTR_EFF_RDTAG_DLY
+#           MBA_DSM0Q_CFG_WRDATA_DLY to use ATTR_EFF_WRDATA_DLY
+
+
+## References for file
+#      /gsa/ausgsa-h3/15/sleung/ekb/
+# Files used to check what target type attributes are
+#      ekb/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+#      ekb/chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml
+#      Example:
+#           <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
+#           <targetType>TARGET_TYPE_MCS</targetType>
+# File used to see if attribute is 1D or 2D array
+#      ekb/output/gen/attribute_ids.H
+#      Example:
+#           typedef uint8_t ATTR_EFF_DIMM_TYPE_Type[2][2];
+# File for finding correct spydef name
+#      /afs/awd.austin.ibm.com/projects/eclipz/lab/p9/vbu_models/n10_e9035_tp035_ec138u51a_soa_sc_u073_01/edc/*.spydef
+#      (File comes from actually building a vbu file and looking at the spydef)
+#      Example:
+#           idial MCP.PORT1.SRQ.PC.MBAREF0Q_CFG_TRFC {
+# Wrapper file calling this
+#      ekb/chips/p9/procedures/hwp/memory/p9_mss_scominit.C
+# Output file generated
+#      ekb/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C
+
+ 
 #--******************************************************************************
 #-- Required keywords/variables
 #--******************************************************************************
@@ -5,18 +61,363 @@
 SyntaxVersion = 3
 
 target_type 0 TARGET_TYPE_MCA;
+target_type 1 TARGET_TYPE_MCBIST;
+target_type 2 TARGET_TYPE_MCS;
+
+define MCBIST = TGT1; # If referencing Attr from mcbist, add "MCBIST." in front
+define MCS = TGT2; # If referencing Attr from mcs, add "MCS." in front
+
+#--******************************************************************************
+#-- Systems Config
+#--******************************************************************************
+
+#--******************************************************************************
+#-- Effective Attributes
+#--******************************************************************************
+
+# PORT INDEX FOR ACCESSING PROPER ENTRY IN ARRAY
+define def_POSITION       =   ATTR_CHIP_UNIT_POS;
+define def_PORT_INDEX     =   def_POSITION % 2;
+
+# define frequency range for potential support of sync mode
+define def_MSS_FREQ_EQ_1866     =   (                                  (MCBIST.ATTR_MSS_FREQ<1867));   
+define def_MSS_FREQ_EQ_2133     =   ((MCBIST.ATTR_MSS_FREQ>=1867)  &&  (MCBIST.ATTR_MSS_FREQ<2134));
+define def_MSS_FREQ_EQ_2400     =   ((MCBIST.ATTR_MSS_FREQ>=2134)  &&  (MCBIST.ATTR_MSS_FREQ<2401));
+define def_MSS_FREQ_EQ_2667     =   ((MCBIST.ATTR_MSS_FREQ>=2667)                                 );
+
+define def_MEM_TYPE_1866_13_13_13   =   def_MSS_FREQ_EQ_1866    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 13 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 13 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 13 );
+define def_MEM_TYPE_1866_14_14_14   =   def_MSS_FREQ_EQ_1866    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 14 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 14 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 14 );
+define def_MEM_TYPE_2133_15_15_15   =   def_MSS_FREQ_EQ_2133    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 15 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 15 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 15 );
+define def_MEM_TYPE_2133_16_16_16   =   def_MSS_FREQ_EQ_2133    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 16 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 16 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 16 );
+define def_MEM_TYPE_2400_16_16_16   =   def_MSS_FREQ_EQ_2400    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 16 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 16 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 16 );
+define def_MEM_TYPE_2400_17_17_17   =   def_MSS_FREQ_EQ_2400    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 17 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 17 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 17 );
+define def_MEM_TYPE_2400_18_18_18   =   def_MSS_FREQ_EQ_2400    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 18 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 18 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 18 );
+define def_MEM_TYPE_2667_18_18_18   =   def_MSS_FREQ_EQ_2667    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 18 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 18 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 18 );
+define def_MEM_TYPE_2667_19_19_19   =   def_MSS_FREQ_EQ_2667    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 19 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 19 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 19 );
+define def_MEM_TYPE_2667_20_20_20   =   def_MSS_FREQ_EQ_2667    &&  ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 20 ) && ( MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX] == 20 ) && ( MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX] == 20 );
 
+define def_NUM_RANKS            = (   MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][0] 
+                                    + MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][1] );
+define def_REFRESH_INTERVAL     =   ((MCS.ATTR_EFF_DRAM_TREFI[def_PORT_INDEX])/(8*def_NUM_RANKS));
+define def_RANK_SWITCH_TCK      =   4 + ((MCBIST.ATTR_MSS_FREQ-1866)/267);         # 1866: 4  2133: 5  2400: 6  2667: 7
+define def_BUS_TURNAROUND_TCK   =   4 + ((MCBIST.ATTR_MSS_FREQ-1866)/267);         # 1866: 4  2133: 5  2400: 6  2667: 7
 
 #--******************************************************************************
-#-- SCOM customization
+#-- Dial Assignments
 #--******************************************************************************
 
-espy MCP.PORT0.SRQ.STD_SIZE [when=S] {
-    spyv;
-    2400_8GB_X4;
+#   TMR0 SCOM REGISTER   #         
+# DRAM TIMING PARAMETERS #
+ 
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_RRDM_DLY [when=S] {      # BL/2+rank_switch
+  spyv;
+  4 + def_RANK_SWITCH_TCK;    
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_RRSMSR_DLY [when=S] {    # tccd_s
+  spyv;
+  # ATTR_EFF_TCCD_S;
+  4;
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_RRSMDR_DLY [when=S] {    # tccd_s
+  spyv;
+  # ATTR_EFF_TCCD_S;
+  4;
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_RROP_DLY [when=S] {      # tccd_l
+  spyv;
+  MCS.ATTR_EFF_DRAM_TCCD_L[def_PORT_INDEX];      
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_WWDM_DLY [when=S] {      # BL/2+rank_switch
+  spyv;
+  4 + def_RANK_SWITCH_TCK;      
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_WWSMSR_DLY [when=S] {    # tccd_s
+  spyv;
+  # ATTR_EFF_TCCD_S;
+  4;
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_WWSMDR_DLY [when=S] {    # tccd_s
+  spyv;
+  # ATTR_EFF_TCCD_S;
+  4;
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_WWOP_DLY [when=S] {      # tccd_l
+  spyv;
+  MCS.ATTR_EFF_DRAM_TCCD_L[def_PORT_INDEX];
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_RWDM_DLY [when=S] {      # (RL+BL/2+turn_around)-WL
+  spyv;
+  MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX];      
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_RWSMSR_DLY [when=S] {    # (RL+BL/2+turn_around)-WL
+  spyv;
+  MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX];    
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_RWSMDR_DLY [when=S] {    # (RL+BL/2+turn_around)-WL
+  spyv;
+  MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX];    
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_WRDM_DLY [when=S] {      # (WL+BL/2+turn_around)-RL
+  spyv;
+  MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX];      
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_WRSMSR_DLY [when=S] {    # WL+BL/2+(Twtr_s/clock period)
+  spyv;
+  MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWTR_S[def_PORT_INDEX];
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR0Q_WRSMDR_DLY [when=S] {    # WL+BL/2+Twtr_s
+  spyv;
+  MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWTR_S[def_PORT_INDEX];
+}
+
+
+#   TMR1 SCOM REGISTER   #         
+# DRAM TIMING PARAMETERS #
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_RRSBG_DLY [when=S] {     # tCCDL
+  spyv;
+  MCS.ATTR_EFF_DRAM_TCCD_L[def_PORT_INDEX];    
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_WRSBG_DLY [when=S] {     # WL+BL/2+Twtr_l
+  spyv;
+  MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWTR_L[def_PORT_INDEX];    
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TFAW [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TFAW[def_PORT_INDEX];    
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TRCD [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX];     
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TRP [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX];      
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TRAS [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRAS[def_PORT_INDEX];     
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_CFG_WR2PRE [when=S] {        # CWL+BL/2+Twr
+  spyv;
+  MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWR[def_PORT_INDEX];
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_CFG_RD2PRE [when=S] {        
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRTP[def_PORT_INDEX];   
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_TRRD [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRRD_S[def_PORT_INDEX];         
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_TRRD_SBG [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRRD_L[def_PORT_INDEX];
+}
+
+ispy  MCP.PORT0.SRQ.MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY [when=S] {
+  spyv, expr;
+  8,                                 (def_MSS_FREQ_EQ_1866==1);
+  9,                                 (def_MSS_FREQ_EQ_2133==1);
+  10,                                (def_MSS_FREQ_EQ_2400==1);
+  11,                                (def_MSS_FREQ_EQ_2667==1);
+}
+
+
+#   DSM0 SCOM REGISTER   #         
+# DRAM TIMING PARAMETERS #
+
+# TODO ANDRE will make ATTR_EFF_RDTAG_DLY a precalculated attribute
+# Can tie this off CL and frequency
+ispy  MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RDTAG_DLY [when=S] {         # ATTR_EFF_DIMM_TYPE:  CDIMM = 0 RDIMM = 1 UDIMM = 2 LRDIMM = 3
+# spyv;
+# 17;  # TEMPORARY since right now we only support 16-16-16 2400
+  spyv, expr;
+  14,                                ((def_MEM_TYPE_1866_13_13_13==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  15,                                ((def_MEM_TYPE_1866_14_14_14==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  16,                                ((def_MEM_TYPE_2133_15_15_15==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  17,                                ((def_MEM_TYPE_2133_16_16_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  17,                                ((def_MEM_TYPE_2400_16_16_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  18,                                ((def_MEM_TYPE_2400_17_17_17==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  19,                                ((def_MEM_TYPE_2400_18_18_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  19,                                ((def_MEM_TYPE_2667_18_18_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  20,                                ((def_MEM_TYPE_2667_19_19_19==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  21,                                ((def_MEM_TYPE_2667_20_20_20==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+                                       
+  16,                                ((def_MEM_TYPE_1866_13_13_13==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  17,                                ((def_MEM_TYPE_1866_14_14_14==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  18,                                ((def_MEM_TYPE_2133_15_15_15==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  19,                                ((def_MEM_TYPE_2133_16_16_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  19,                                ((def_MEM_TYPE_2400_16_16_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  20,                                ((def_MEM_TYPE_2400_17_17_17==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  21,                                ((def_MEM_TYPE_2400_18_18_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  21,                                ((def_MEM_TYPE_2667_18_18_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  22,                                ((def_MEM_TYPE_2667_19_19_19==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  23,                                ((def_MEM_TYPE_2667_20_20_20==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+}
+     
+# TODO ANDRE will make ATTR_EFF_WRDATA_DLY a precalculated attribute
+ispy  MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WRDATA_DLY [when=S] {
+# spyv;
+# 5;  # TEMPORARY since right now we only support 16-16-16 2400
+  spyv, expr;
+  3,                                 ((def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  4,                                 ((def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  5,                                 ((def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+  6,                                 ((def_MSS_FREQ_EQ_2667==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1));
+                                       
+  2,                                 ((def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  3,                                 ((def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  4,                                 ((def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+  5,                                 ((def_MSS_FREQ_EQ_2667==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3));
+}
+
+ispy  MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WRDONE_DLY [when=S] {
+  spyv;
+  24;    
+}
+
+ispy  MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RODT_START_DLY [when=S] {
+  spyv, expr;
+   4,                                (def_MEM_TYPE_1866_13_13_13==1);
+   5,                                (def_MEM_TYPE_1866_14_14_14==1);
+   6,                                (def_MEM_TYPE_2133_15_15_15==1);
+   7,                                (def_MEM_TYPE_2133_16_16_16==1);
+   7,                                (def_MEM_TYPE_2400_16_16_16==1);
+   8,                                (def_MEM_TYPE_2400_17_17_17==1);
+   9,                                (def_MEM_TYPE_2400_18_18_18==1);
+   9,                                (def_MEM_TYPE_2667_18_18_18==1);
+  10,                                (def_MEM_TYPE_2667_19_19_19==1);
+  11,                                (def_MEM_TYPE_2667_20_20_20==1);
+}
+
+ispy  MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RODT_END_DLY [when=S] {
+  spyv, expr;
+   9,                                (def_MEM_TYPE_1866_13_13_13==1);
+  10,                                (def_MEM_TYPE_1866_14_14_14==1);
+  11,                                (def_MEM_TYPE_2133_15_15_15==1);
+  12,                                (def_MEM_TYPE_2133_16_16_16==1);
+  12,                                (def_MEM_TYPE_2400_16_16_16==1);
+  13,                                (def_MEM_TYPE_2400_17_17_17==1);
+  14,                                (def_MEM_TYPE_2400_18_18_18==1);
+  14,                                (def_MEM_TYPE_2667_18_18_18==1);
+  15,                                (def_MEM_TYPE_2667_19_19_19==1);
+  16,                                (def_MEM_TYPE_2667_20_20_20==1);
 }
 
-espy MCP.PORT0.SRQ.STD_TIMING [when=S] {
-    spyv;
-    SC_DDR4_2400_16_16_16R;
+ispy  MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WODT_START_DLY [when=S] {
+  spyv;
+   1;
 }
+
+ispy  MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WODT_END_DLY [when=S] {
+  spyv;
+   6;
+}
+
+#  FARB0 SCOM REGISTER   #         
+
+espy  MCP.PORT0.SRQ.MBA_FARB0Q_CFG_PARITY_AFTER_CMD [when=S] {
+  spyv;
+  ON;
+}
+
+#  REF0 SCOM REGISTER    #         
+
+#gdial std_size 4gbx4 (8GB rank)          
+
+ispy  MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_REFRESH_INTERVAL [when=S] {
+  spyv;
+  def_REFRESH_INTERVAL;
+}
+
+ispy  MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_TRFC [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRFC[def_PORT_INDEX];
+}
+
+ispy  MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_REFR_TSV_STACK [when=S] {
+  spyv;
+  MCS.ATTR_EFF_DRAM_TRFC_DLR[def_PORT_INDEX];
+}
+
+#  RPC0 SCOM REGISTER    #         
+
+ispy  MCP.PORT0.SRQ.PC.MBARPC0Q_CFG_PUP_PDN [when=S] {         # tCKE
+  spyv, expr;
+  5,                                 (def_MSS_FREQ_EQ_1866==1);
+  6,                                 (def_MSS_FREQ_EQ_2133==1);
+  6,                                 (def_MSS_FREQ_EQ_2400==1);
+  7,                                 (def_MSS_FREQ_EQ_2667==1);
+}
+
+ispy  MCP.PORT0.SRQ.PC.MBARPC0Q_CFG_PDN_PUP [when=S] {         # tPD
+  spyv, expr;
+  5,                                 (def_MSS_FREQ_EQ_1866==1);
+  6,                                 (def_MSS_FREQ_EQ_2133==1);
+  6,                                 (def_MSS_FREQ_EQ_2400==1);
+  7,                                 (def_MSS_FREQ_EQ_2667==1);
+}
+
+ispy  MCP.PORT0.SRQ.PC.MBARPC0Q_CFG_PUP_AVAIL [when=S] {       # tXP
+  spyv, expr;
+  6,                                 (def_MSS_FREQ_EQ_1866==1);
+  7,                                 (def_MSS_FREQ_EQ_2133==1);
+  8,                                 (def_MSS_FREQ_EQ_2400==1);
+  9,                                 (def_MSS_FREQ_EQ_2667==1);
+}
+
+#  STR0 SCOM REGISTER    #         
+
+ispy  MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TCKSRE [when=S] {
+  spyv, expr;
+  10,                                (def_MSS_FREQ_EQ_1866==1);
+  11,                                (def_MSS_FREQ_EQ_2133==1);
+  12,                                (def_MSS_FREQ_EQ_2400==1);
+  14,                                (def_MSS_FREQ_EQ_2667==1);
+}
+
+ispy  MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TCKSRX [when=S] {
+  spyv, expr;
+  10,                                (def_MSS_FREQ_EQ_1866==1);
+  11,                                (def_MSS_FREQ_EQ_2133==1);
+  12,                                (def_MSS_FREQ_EQ_2400==1);
+  14,                                (def_MSS_FREQ_EQ_2667==1);
+}
+
+ispy  MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TCKESR [when=S] {
+  spyv;
+  5;
+}
+
+ispy  MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TXSDLL [when=S] {
+  spyv, expr;
+  597,                               (def_MSS_FREQ_EQ_1866==1);
+  768,                               (def_MSS_FREQ_EQ_2133==1);
+  768,                               (def_MSS_FREQ_EQ_2400==1);
+  939,                               (def_MSS_FREQ_EQ_2667==1);
+}
+
+