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| author | Shelton Leung <sleung@us.ibm.com> | 2016-12-21 16:10:45 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-01-04 17:33:35 -0500 |
| commit | 9f73dc110327b825e69d6ae33b8e41bac8f4553d (patch) | |
| tree | dab272c83b576eff9644f0f5b0960949f88eeece /src/import/chips/p9/initfiles | |
| parent | 1f98fdcc76cdc508ede4100d273d8884fe52b692 (diff) | |
| download | talos-hostboot-9f73dc110327b825e69d6ae33b8e41bac8f4553d.tar.gz talos-hostboot-9f73dc110327b825e69d6ae33b8e41bac8f4553d.zip | |
Set safe refresh to same as normal refresh
Change-Id: Iea10b30e0e99f8002d3df0c420f46d1cb6d1c593
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34153
Dev-Ready: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34155
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/initfiles')
| -rw-r--r-- | src/import/chips/p9/initfiles/p9.mca.scom.initfile | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile index cbcd70b4c..e8476c67e 100644 --- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile @@ -381,6 +381,7 @@ ispy MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_REFR_TSV_STACK [when=S] { MCS.ATTR_EFF_DRAM_TRFC_DLR[def_PORT_INDEX]; } + # RPC0 SCOM REGISTER # ispy MCP.PORT0.SRQ.PC.MBARPC0Q_CFG_PUP_PDN [when=S] { # tCKE @@ -438,6 +439,13 @@ ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TXSDLL [when=S] { 939, (def_MSS_FREQ_EQ_2667==1); } +# Make Safe Refresh Match Refresh Interval +ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL [when=S] { + spyv; + def_REFRESH_INTERVAL; +} + + # CID # Slot 0 ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S0_CID [when=S] { |
