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| author | Shelton Leung <sleung@us.ibm.com> | 2016-11-17 10:45:03 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-12-05 18:32:08 -0500 |
| commit | 892b323572beb7a117df4e85e504e85753864c2b (patch) | |
| tree | fd22eaff1aa3f742bfd527da95f84e89069f22de /src/import/chips/p9/initfiles | |
| parent | 1a6584dc8d8e064c0fd2152cd9135e7ddf07de8a (diff) | |
| download | talos-hostboot-892b323572beb7a117df4e85e504e85753864c2b.tar.gz talos-hostboot-892b323572beb7a117df4e85e504e85753864c2b.zip | |
scan inits for lab workaround for DI bug HW392781
Change-Id: Ia71c4d0933112c6804774b76a08ec5fbbe254833
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32780
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32784
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/initfiles')
| -rw-r--r-- | src/import/chips/p9/initfiles/p9.mc.scan.initfile | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9.mc.scan.initfile b/src/import/chips/p9/initfiles/p9.mc.scan.initfile index 4a9c0d925..d93e92108 100644 --- a/src/import/chips/p9/initfiles/p9.mc.scan.initfile +++ b/src/import/chips/p9/initfiles/p9.mc.scan.initfile @@ -78,3 +78,39 @@ ispy MC23.PORT3.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] { spyv; 8; } + + +# WORKAROUND FOR HW375544 / HW392781 + +ispy MC01.PORT0.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} +ispy MC01.PORT1.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} +ispy MC01.PORT2.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} +ispy MC01.PORT3.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} +ispy MC23.PORT0.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} +ispy MC23.PORT1.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} +ispy MC23.PORT2.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} +ispy MC23.PORT3.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] { + spyv; + 0b1; +} |
