mc epsilon formula fix

Change-Id: I42256405774cbb8fa181e740cf737b6e5d9fa098
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36565
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36641
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 42 insertions, 18 deletions

diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
index 8ff837ba8..d203a7894 100644
--- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile
+++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
@@ -130,6 +130,26 @@ define def_SLOT0_DRAM_STACK_HEIGHT = (   MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_POR
 define def_SLOT1_DRAM_STACK_HEIGHT = (   MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][1]
                                          / def_SLOT1_DENOMINATOR );
 
+# Epsilon Related
+#    There is a 4 window variance of actual wait for each setting x
+#       (Because implemented with a 4 cycle free running timebase)
+#       The Window: 4x-3 <= Actual wait <= 4x
+#    The attribute ATTR_PROC_EPS_READ_CYCLES_T# represents min wait required
+#    Entire window of possible actual waits must be > required wait
+#       Working this out in a table
+#          EPS NEEDED | SETTING | RESULTANT WAIT
+#              5      |    2    |   5 -  8      
+#              6      |    3    |   9 - 12      
+#              7      |    3    |   9 - 12      
+#              8      |    3    |   9 - 12      
+#              9      |    3    |   9 - 12      
+#             10      |    4    |  13 - 16      
+#       Resulting formula: setting = ( required + 6 ) / 4
+
+define def_MC_EPSILON_CFG_T0 = ( SYS.ATTR_PROC_EPS_READ_CYCLES_T0 + 6 ) / 4;
+define def_MC_EPSILON_CFG_T1 = ( SYS.ATTR_PROC_EPS_READ_CYCLES_T1 + 6 ) / 4;
+define def_MC_EPSILON_CFG_T2 = ( SYS.ATTR_PROC_EPS_READ_CYCLES_T2 + 6 ) / 4;
+
 #--******************************************************************************
 #-- Dial Assignments
 #--******************************************************************************
@@ -667,19 +687,6 @@ ispy MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RRQ_FIFO_MODE [when=S] {
   MCBIST.ATTR_MSS_REORDER_QUEUE_SETTING;
 }
 
-
-
-####################################################
-# DD1 WORKAROUNDS
-####################################################
-
-# Force clock enable high DD1 Periodics Issue
-
-espy  MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OE_ALWAYS_ON [when=S]{
-  spyv;
-  ON;
-}
-
 # Epsilon Settings per Power Bus Spreadsheet
 
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON [when=S] {
@@ -689,27 +696,44 @@ ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON [when=S] {
 
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_LOCAL_NODE_EPSILON [when=S] {
   spyv;
-  SYS.ATTR_PROC_EPS_READ_CYCLES_T0 / 4;
+  # tier 0
+  def_MC_EPSILON_CFG_T0;
 }
 
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_NEAR_NODAL_EPSILON [when=S] {
   spyv;
-  SYS.ATTR_PROC_EPS_READ_CYCLES_T1 / 4;
+  # tier 1
+  def_MC_EPSILON_CFG_T1;
 }
 
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_REMOTE_NODAL_EPSILON [when=S] {
   spyv;
-  SYS.ATTR_PROC_EPS_READ_CYCLES_T2 / 4;
+  # tier 2
+  def_MC_EPSILON_CFG_T2;
 }
 
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_GROUP_EPSILON [when=S] {
   spyv;
-  SYS.ATTR_PROC_EPS_READ_CYCLES_T1 / 4;
+  # tier 1
+  def_MC_EPSILON_CFG_T1;
 }
 
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON [when=S] {
   spyv;
-  SYS.ATTR_PROC_EPS_READ_CYCLES_T2 / 4;
+  # tier 2
+  def_MC_EPSILON_CFG_T2;
+}
+
+
+####################################################
+# DD1 WORKAROUNDS
+####################################################
+
+# Force clock enable high DD1 Periodics Issue
+
+espy  MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OE_ALWAYS_ON [when=S]{
+  spyv;
+  ON;
 }
 
 # HW366164 - SRQ Fullness Control