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| author | Shelton Leung <sleung@us.ibm.com> | 2017-05-11 16:08:59 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-05-22 23:56:16 -0400 |
| commit | 490882657a26e4aa662ef2515c38e443ca3c506e (patch) | |
| tree | ae9719e96267f58c86739e5918852594aafe996f /src/import/chips/p9/initfiles | |
| parent | e60e1d2e548b06d43165c60365d184bb3ffc3f34 (diff) | |
| download | talos-hostboot-490882657a26e4aa662ef2515c38e443ca3c506e.tar.gz talos-hostboot-490882657a26e4aa662ef2515c38e443ca3c506e.zip | |
additional dd2 nimbus inits
Change-Id: I00487a727859a8c3311dcdad1da80d02c94a62a7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40416
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40420
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/initfiles')
| -rw-r--r-- | src/import/chips/p9/initfiles/p9.mca.scom.initfile | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile index 99cf91bf7..4ff487428 100644 --- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile @@ -1084,6 +1084,31 @@ espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_ENABLE_REFRESH_BLOCK_DISP [when=S && ATTR OFF; } +espy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_ENABLE_BUSY_COUNTERS [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { + spyv; + ON; +} + +espy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { + spyv; + 1024_CYCLES; +} + +ispy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD0 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { + spyv; + 38; +} + +ispy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD1 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { + spyv; + 51; +} + +ispy MC01.PORT0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD2 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { + spyv; + 64; +} + ################# # DD2 WORKAROUNDS ################# @@ -1103,3 +1128,8 @@ espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CL0 [when=S && ATTR_CHIP_EC_FEATUR ON; } +# When AMO cache is re-enabled for DD2, we need to run with write open page disabled (same CQ observation) +espy MCP.PORT0.SRQ.MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE [when=S && !ATTR_CHIP_EC_FEATURE_HW401780] { + spyv; + ON; +} |
