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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-08-18 10:53:44 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-29 11:39:24 -0400 |
| commit | 2b881ebf90218af1ce41918b214498c2574940e1 (patch) | |
| tree | 5acce76de62c874ae32eff6c12d3ffa1094fc44f /src/import/chips/p9/initfiles | |
| parent | 598111fc4b49f16495b41b8461fc01d49239eb42 (diff) | |
| download | talos-hostboot-2b881ebf90218af1ce41918b214498c2574940e1.tar.gz talos-hostboot-2b881ebf90218af1ce41918b214498c2574940e1.zip | |
Adds DDR4 hybrid NV-RDIMM support
Change-Id: Ie5cc0ed4dc6337c35df2e222cc4e220e5720f0bd
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44974
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45182
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/initfiles')
| -rw-r--r-- | src/import/chips/p9/initfiles/p9n.mca.scom.initfile | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/import/chips/p9/initfiles/p9n.mca.scom.initfile b/src/import/chips/p9/initfiles/p9n.mca.scom.initfile index 4cd2779a6..1b5eddf9b 100644 --- a/src/import/chips/p9/initfiles/p9n.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9n.mca.scom.initfile @@ -23,7 +23,7 @@ #--****************************************************************************** #-- REFERENCES FOR FILE (note: exact paths may move) #--****************************************************************************** -# Files used to check what target type attributes are +# Files used to check what target type attributes are # ekb/chips/p9/procedures/xml/attribute_info/*.xml # Example: # <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id> @@ -128,12 +128,12 @@ define def_SLOT1_DRAM_STACK_HEIGHT = ( MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_POR # Entire window of possible actual waits must be > required wait # Working this out in a table # EPS NEEDED | SETTING | RESULTANT WAIT -# 5 | 2 | 5 - 8 -# 6 | 3 | 9 - 12 -# 7 | 3 | 9 - 12 -# 8 | 3 | 9 - 12 -# 9 | 3 | 9 - 12 -# 10 | 4 | 13 - 16 +# 5 | 2 | 5 - 8 +# 6 | 3 | 9 - 12 +# 7 | 3 | 9 - 12 +# 8 | 3 | 9 - 12 +# 9 | 3 | 9 - 12 +# 10 | 4 | 13 - 16 # Resulting formula: setting = ( required + 6 ) / 4 define def_MC_EPSILON_CFG_T0 = ( SYS.ATTR_PROC_EPS_READ_CYCLES_T0 + 6 ) / 4; @@ -287,7 +287,7 @@ ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RDTAG_DLY [when=S] { # ATTR_EFF_DIMM_T spyv, expr; # 1/17/2017 INITIAL CONCEPT (HAS SINCE BEEN ADJUSTED): - # rdtag_dly + 3 + rdptrdly > PHY DELAY + CL + # rdtag_dly + 3 + rdptrdly > PHY DELAY + CL # rdtag_dly > PHY DELAY + CL - 3 - rdptrdly # PHY DELAY = 12 for 1866 and 2133, 13 for 2400 and 2666, +1 for LRDIMM # rdptrdly = 1 @@ -755,7 +755,7 @@ ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON [when=S] { # New values 6/13/2017 in light of HW413361 # L T D dn h | m/n min m/n max # --------------------------------------------- -# 5 2(off) 1 0(off) 0(off) | SYNC +# 5 2(off) 1 0(off) 0(off) | SYNC # 3 3(on) 1 0(off) 0(off) | 727 915 # 4 3(on) 1 0(off) 0(off) | 915 1040 # 4 3(on) 0 0(off) 0(off) | 1040 1150 @@ -810,11 +810,11 @@ espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE # "L" field ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] { spyv, expr; - 5, (PROC.ATTR_MC_SYNC_MODE==1); + 5, (PROC.ATTR_MC_SYNC_MODE==1); 3, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio < 915); 4, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 915) && (def_mn_freq_ratio < 1150); 5, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1150) && (def_mn_freq_ratio < 1300); - 6, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1300); + 6, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1300); } # "T" field (new for DD2) @@ -827,21 +827,21 @@ espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && !ATTR_CHIP_EC_F # "D" field ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] { spyv, expr; - 1, (PROC.ATTR_MC_SYNC_MODE==1); + 1, (PROC.ATTR_MC_SYNC_MODE==1); 1, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio < 1040); 0, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1040) && (def_mn_freq_ratio < 1150); 1, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1150) && (def_mn_freq_ratio < 1215); 0, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1215) && (def_mn_freq_ratio < 1300); 1, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1300) && (def_mn_freq_ratio < 1400); - 0, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1400); + 0, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1400); } # "dn" field espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] { spyv, expr; - OFF, (PROC.ATTR_MC_SYNC_MODE==1); + OFF, (PROC.ATTR_MC_SYNC_MODE==1); OFF, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio < 1215); - ON, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1215); + ON, (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1215); } # "h" field |
