Initial release for p9_scominfo HWP

MCBIST/NPU fixes
Shift location in EKB
Add makefile for test utility

Change-Id: Ibd2732da4a9b43020516bfd895dec6f84f202d27
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20316
Tested-by: Jenkins Server
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23103
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 986 insertions, 0 deletions

diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H
new file mode 100644
index 000000000..b10d424a9
--- /dev/null
+++ b/src/import/chips/p9/common/scominfo/p9_cu.H
@@ -0,0 +1,80 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: systems/power9/procedures/p9_cu.H $                           */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_cu.H
+/// @brief P9 chip unit definitions
+///
+/// HWP HWP Owner: jmcgill@us.ibm.com
+/// HWP FW Owner: dcrowell@us.ibm.com
+/// HWP Team: Infrastructure
+/// HWP Level: 1
+/// HWP Consumed by: FSP/HB
+///
+
+#ifndef P9_CU_H
+#define P9_CU_H
+
+// includes
+#include <stdint.h>
+
+extern "C"
+{
+    /// P9 chip unit type enumeration
+    typedef enum
+    {
+        P9C_CHIP,            ///< Cumulus chip (included for future expansion)
+        P9N_CHIP,            ///< Nimbus chip (included for future expansion)
+        PU_C_CHIPUNIT,       ///< Core
+        PU_EQ_CHIPUNIT,      ///< Quad
+        PU_EX_CHIPUNIT,      ///< EX
+        PU_XBUS_CHIPUNIT,    ///< XBUS
+        PU_OBUS_CHIPUNIT,    ///< OBUS
+        PU_NVBUS_CHIPUNIT,   ///< NV Link Brick
+        PU_PEC_CHIPUNIT,     ///< PCIe (PEC)
+        PU_PHB_CHIPUNIT,     ///< PCIe (PHB)
+        PU_MI_CHIPUNIT,      ///< MI (Cumulus only)
+        PU_DMI_CHIPUNIT,     ///< DMI (Cumulus only)
+        PU_MCS_CHIPUNIT,     ///< MCS (Nimbus only)
+        PU_MCA_CHIPUNIT,     ///< MCA (Nimbus only)
+        PU_MCBIST_CHIPUNIT,  ///< MCBIST (Nimbus only)
+        PU_OCC_CHIPUNIT,     ///< OCC
+        PU_PERV_CHIPUNIT,    ///< Pervasive
+        PU_PPE_CHIPUNIT,     ///< PPE
+        PU_SBE_CHIPUNIT,     ///< SBE
+        PU_CAPP_CHIPUNIT,    ///< CAPP
+        NONE                 ///< None/Invalid
+    } p9ChipUnits_t;
+
+    /// P9 chip unit pairing struct
+    struct p9_chipUnitPairing_t
+    {
+        /// @brief Default constructor
+        p9_chipUnitPairing_t()
+            : chipUnitType(NONE), chipUnitNum(0) {}
+        /// @brief Construct from type/instance number
+        p9_chipUnitPairing_t (p9ChipUnits_t type, uint32_t num)
+            : chipUnitType(type), chipUnitNum(num) {}
+
+        p9ChipUnits_t chipUnitType;  ///< chip unit type
+        uint32_t chipUnitNum;        ///< chip unit instance number
+    };
+
+} // extern "C"
+
+#endif /* P9_CU_H */
diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
new file mode 100644
index 000000000..ee4efecc0
--- /dev/null
+++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
@@ -0,0 +1,450 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: systems/power9/procedures/p9_scom_addr.H $                    */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_cu.H
+/// @brief P9 chip unit definitions
+///
+/// HWP HWP Owner: jmcgill@us.ibm.com
+/// HWP FW Owner: dcrowell@us.ibm.com
+/// HWP Team: Infrastructure
+/// HWP Level: 1
+/// HWP Consumed by: FSP/HB
+///
+
+#ifndef P9_SCOM_ADDR_H
+#define P9_SCOM_ADDR_H
+
+// includes
+#include <stdint.h>
+
+extern "C"
+{
+    /// P9 Chiplet ID enumeration
+    typedef enum
+    {
+        PIB_CHIPLET_ID  = 0x00,     ///< PIB chiplet
+        PERV_CHIPLET_ID = 0x01,     ///< TP chiplet
+        N0_CHIPLET_ID   = 0x02,     ///< Nest0 (North) chiplet
+        N1_CHIPLET_ID   = 0x03,     ///< Nest1 (East) chiplet
+        N2_CHIPLET_ID   = 0x04,     ///< Nest2 (South) chiplet
+        N3_CHIPLET_ID   = 0x05,     ///< Nest3 (West) chiplet
+        XB_CHIPLET_ID   = 0x06,     ///< XBus chiplet
+        MC01_CHIPLET_ID = 0x07,     ///< MC01 (West) chiplet
+        MC23_CHIPLET_ID = 0x08,     ///< MC23 (East) chiplet
+        OB0_CHIPLET_ID  = 0x09,     ///< OBus0 chiplet
+        OB1_CHIPLET_ID  = 0x0A,     ///< OBus1 chiplet (Cumulus only)
+        OB2_CHIPLET_ID  = 0x0B,     ///< OBus2 chiplet (Cumulus only)
+        OB3_CHIPLET_ID  = 0x0C,     ///< OBus3 chiplet
+        PCI0_CHIPLET_ID = 0x0D,     ///< PCIe0 chiplet
+        PCI1_CHIPLET_ID = 0x0E,     ///< PCIe1 chiplet
+        PCI2_CHIPLET_ID = 0x0F,     ///< PCIe2 chiplet
+        EP00_CHIPLET_ID = 0x10,     ///< Quad0 chiplet (EX0/1)
+        EP01_CHIPLET_ID = 0x11,     ///< Quad1 chiplet (EX2/3)
+        EP02_CHIPLET_ID = 0x12,     ///< Quad2 chiplet (EX4/5)
+        EP03_CHIPLET_ID = 0x13,     ///< Quad3 chiplet (EX6/7)
+        EP04_CHIPLET_ID = 0x14,     ///< Quad4 chiplet (EX8/9)
+        EP05_CHIPLET_ID = 0x15,     ///< Quad5 chiplet (EX10/11)
+        EC00_CHIPLET_ID = 0x20,     ///< Core0 chiplet (Quad0, EX0, C0)
+        EC01_CHIPLET_ID = 0x21,     ///< Core1 chiplet (Quad0, EX0, C1)
+        EC02_CHIPLET_ID = 0x22,     ///< Core2 chiplet (Quad0, EX1, C0)
+        EC03_CHIPLET_ID = 0x23,     ///< Core3 chiplet (Quad0, EX1, C1)
+        EC04_CHIPLET_ID = 0x24,     ///< Core4 chiplet (Quad1, EX2, C0)
+        EC05_CHIPLET_ID = 0x25,     ///< Core5 chiplet (Quad1, EX2, C1)
+        EC06_CHIPLET_ID = 0x26,     ///< Core6 chiplet (Quad1, EX3, C0)
+        EC07_CHIPLET_ID = 0x27,     ///< Core7 chiplet (Quad1, EX3, C1)
+        EC08_CHIPLET_ID = 0x28,     ///< Core8 chiplet (Quad2, EX4, C0)
+        EC09_CHIPLET_ID = 0x29,     ///< Core9 chiplet (Quad2, EX4, C1)
+        EC10_CHIPLET_ID = 0x2A,     ///< Core10 chiplet (Quad2, EX5, C0)
+        EC11_CHIPLET_ID = 0x2B,     ///< Core11 chiplet (Quad2, EX5, C1)
+        EC12_CHIPLET_ID = 0x2C,     ///< Core12 chiplet (Quad3, EX6, C0)
+        EC13_CHIPLET_ID = 0x2D,     ///< Core13 chiplet (Quad3, EX6, C1)
+        EC14_CHIPLET_ID = 0x2E,     ///< Core14 chiplet (Quad3, EX7, C0)
+        EC15_CHIPLET_ID = 0x2F,     ///< Core15 chiplet (Quad3, EX7, C1)
+        EC16_CHIPLET_ID = 0x30,     ///< Core16 chiplet (Quad4, EX8, C0)
+        EC17_CHIPLET_ID = 0x31,     ///< Core17 chiplet (Quad4, EX8, C1)
+        EC18_CHIPLET_ID = 0x32,     ///< Core18 chiplet (Quad4, EX9, C0)
+        EC19_CHIPLET_ID = 0x33,     ///< Core19 chiplet (Quad4, EX9, C1)
+        EC20_CHIPLET_ID = 0x34,     ///< Core20 chiplet (Quad5, EX10, C0)
+        EC21_CHIPLET_ID = 0x35,     ///< Core21 chiplet (Quad5, EX10, C1)
+        EC22_CHIPLET_ID = 0x36,     ///< Core22 chiplet (Quad5, EX11, C0)
+        EC23_CHIPLET_ID = 0x37      ///< Core23 chiplet (Quad5, EX11, C1)
+    } p9_chiplet_id_t;
+
+    /// P9 SCOM port ID enumeration
+    typedef enum
+    {
+        GPREG_PORT_ID = 0x0,        ///< GP registers
+        UNIT_PORT_ID = 0x1,         ///< Functional registers
+        CME_PORT_ID = 0x2,          ///< CME registers
+        CC_PORT_ID = 0x3,           ///< Clock control registers
+        FIR_PORT_ID = 0x4,          ///< Common FIR registers
+        CPM_PORT_ID = 0x5,          ///< CPM registers
+        PCBSLV_PORT_ID = 0xF        ///< PCB Slave registers
+    } p9_port_id_t;
+
+    /// P9 Core chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_core_top.vhdl
+    typedef enum
+    {
+        EC_PERV_RING_ID = 0x1,      ///< PERV
+        EC_PC_0_RING_ID = 0x2,      ///< PC_0
+        EC_PC_1_RING_ID = 0x3,      ///< PC_1
+        EC_PC_2_RING_ID = 0x4,      ///< PC_2
+        EC_PC_3_RING_ID = 0x5       ///< PC_3
+    } p9_ec_ring_id_t;
+
+    /// P9 Quad chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_l3_top.vhdl
+    typedef enum
+    {
+        EQ_PERV_RING_ID = 0x1,      ///< PERV
+        EQ_L2_0_RING_ID = 0x2,      ///< L2_0
+        EQ_L2_1_RING_ID = 0x3,      ///< L2_1
+        EQ_NC_0_RING_ID = 0x4,      ///< NC_0
+        EQ_NC_1_RING_ID = 0x5,      ///< NC_1
+        EQ_L3_0_RING_ID = 0x6,      ///< L3_0
+        EQ_L3_1_RING_ID = 0x7,      ///< L3_1
+        EQ_CME_0_RING_ID = 0x9,     ///< CME_0
+        EQ_CME_1_RING_ID = 0xA,     ///< CME_1
+        EQ_L2_0_TRA_RING_ID = 0xB,  ///< L2_0_TRA
+        EQ_L2_1_TRA_RING_ID = 0xC   ///< L2_1_TRA
+    } p9_eq_ring_id_t;
+
+    /// P9 N0 chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_n0_top.vhdl
+    typedef enum
+    {
+        N0_PERV_RING_ID = 0x1,      ///< PERV
+        N0_CXA0_0_RING_ID = 0x2,    ///< CXA0_0
+        N0_NX_0_RING_ID = 0x4,      ///< NX_0
+        N0_PBIOE0_0_RING_ID = 0x6,  ///< PBIOE0_0
+        N0_PBIOE1_0_RING_ID = 0x7,  ///< PBIOE1_0
+        N0_PBIOE2_0_RING_ID = 0x8   ///< PBIOE2_0
+    } p9_n0_ring_id_t;
+
+    /// P9 N1 chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_n1_top.vhdl
+    typedef enum
+    {
+        N1_PERV_RING_ID = 0x1,      ///< PERV
+        N1_MC23_0_RING_ID = 0x2,    ///< MC23_0
+        N1_MCD_0_RING_ID = 0x4,     ///< MCD_0
+        N1_MCD_1_RING_ID = 0x5,     ///< MCD_1
+        N1_VA_0_RING_ID = 0x6       ///< VA_0
+    } p9_n1_ring_id_t;
+
+    /// P9 N2 chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_n2_top.vhdl
+    typedef enum
+    {
+        N2_PERV_RING_ID = 0x1,      ///< PERV
+        N2_CXA1_0_RING_ID = 0x2,    ///< CXA1_0
+        N2_PCIS0_0_RING_ID = 0x3,   ///< PCIS0_0
+        N2_PCIS1_0_RING_ID = 0x4,   ///< PCIS1_0
+        N2_PCIS2_0_RING_ID = 0x5,   ///< PCIS2_0
+        N2_IOPSI_0_RING_ID = 0x6    ///< IOPSI_0
+    } p9_n2_ring_id_t;
+
+    typedef enum
+    {
+        PEC_SAT_ID = 0x0
+    } p9_pec_sat_id_t;
+
+    /// P9 N3 chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_n3_top.vhdl
+    typedef enum
+    {
+        N3_PERV_RING_ID = 0x1,      ///< PERV
+        N3_MC01_0_RING_ID = 0x2,    ///< MC01_0
+        N3_NPU_0_RING_ID = 0x4,     ///< NPU_0
+        N3_NPU_1_RING_ID = 0x5,     ///< NPU_1
+        N3_PB_0_RING_ID = 0x6,      ///< PB_0
+        N3_PB_1_RING_ID = 0x7,      ///< PB_1
+        N3_PB_2_RING_ID = 0x8,      ///< PB_2
+        N3_PB_3_RING_ID = 0x9,      ///< PB_3
+        N3_BR_0_RING_ID = 0xa,      ///< BR_0
+        N3_MM_0_RING_ID = 0xb,      ///< MM_0
+        N3_INT_0_RING_ID = 0xc,     ///< INT_0
+        N3_PB_4_RING_ID = 0xd,      ///< PB_4
+        N3_PB_5_RING_ID = 0xe,      ///< PB_5
+    } p9_n3_ring_id_t;
+
+    /// P9 XBUS chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_xb_top.vhdl
+    typedef enum
+    {
+        XB_PERV_RING_ID = 0x1,      ///< PERV
+        XB_IOPPE_0_RING_ID = 0x2,   ///< IOPPE
+        XB_IOX_0_RING_ID = 0x3,     ///< IOX_0
+        XB_IOX_1_RING_ID = 0x4,     ///< IOX_1
+        XB_IOX_2_RING_ID = 0x5,     ///< IOX_2
+        XB_PBIOX_0_RING_ID = 0x6,   ///< PBIOX_0
+        XB_PBIOX_1_RING_ID = 0x7,   ///< PBIOX_1
+        XB_PBIOX_2_RING_ID = 0x8    ///< PBIOX_2
+    } p9_xb_ring_id_t;
+
+    typedef enum
+    {
+        XB_PB_SAT_ID = 0x0
+    } p9_xb_pb_sat_id_t;
+
+    typedef enum
+    {
+        XB_IOF_SAT_ID = 0x0,
+        XB_PPE_SAT_ID = 0x1
+    } p9_xb_iof_sat_id_t;
+
+    /// P9 MC chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_mcslow_top.vhdl
+#ifdef MC_E9022
+    typedef enum
+    {
+        MC_PERV_RING_ID = 0x1,      ///< PERV
+        MC_MC01_0_RING_ID = 0x2,    ///< MC01_0 / MC23_0
+        MC_MCTRA_0_RING_ID = 0x3,   ///< MCTRA01_0 / MCTRA23_0
+        MC_IOM0_0_RING_ID = 0x4,    ///< IOM01_0 / IOM45_0
+        MC_IOM0_1_RING_ID = 0x5,    ///< IOM01_1 / IOM45_1
+        MC_IOM1_0_RING_ID = 0x6,    ///< IOM01_2 / IOM45_2
+        MC_IOM1_1_RING_ID = 0x7,    ///< IOM01_3 / IOM45_3
+        MC_IOM2_0_RING_ID = 0x8,    ///< IOM23_0 / IOM67_0
+        MC_IOM2_1_RING_ID = 0x9,    ///< IOM23_1 / IOM67_1
+        MC_IOM3_0_RING_ID = 0xa,    ///< IOM23_2 / IOM67_2
+        MC_IOM3_1_RING_ID = 0xb     ///< IOM23_3 / IOM67_3
+    } p9_mc_ring_id_t;
+#else
+    typedef enum
+    {
+        MC_PERV_RING_ID = 0x1,      ///< PERV
+        MC_MC01_0_RING_ID = 0x2,    ///< MC01_0 / MC23_0
+        MC_MCTRA_0_RING_ID = 0x3,   ///< MCTRA01_0 / MCTRA23_0
+        MC_IOM01_0_RING_ID = 0x4,   ///< IOM01_0 / IOM45_0
+        MC_IOM01_1_RING_ID = 0x5,   ///< IOM01_1 / IOM45_1
+        MC_IOM23_0_RING_ID = 0x6,   ///< IOM23_0 / IOM67_0
+        MC_IOM23_1_RING_ID = 0x7,   ///< IOM23_1 / IOM67_1
+        MC_MC01_1_RING_ID = 0x8,    ///< MC01_1 / MC23_1
+    } p9_mc_ring_id_t;
+#endif
+
+    typedef enum
+    {
+        MC_DIR_SAT_ID_PBI_01 = 0x0,
+        MC_DIR_SAT_ID_PBI_23 = 0x2,
+        MC_DIR_SAT_ID_SRQ_0 = 0x4,
+        MC_DIR_SAT_ID_SRQ_1 = 0x5,
+        MC_DIR_SAT_ID_SRQ_2 = 0x6,
+        MC_DIR_SAT_ID_SRQ_3 = 0x7,
+        MC_DIR_SAT_ID_ECC64_0 = 0x8,
+        MC_DIR_SAT_ID_ECC64_1 = 0x9,
+        MC_DIR_SAT_ID_ECC64_2 = 0xa,
+        MC_DIR_SAT_ID_ECC64_3 = 0xb,
+    } p9_mc_dir0_sat_id_t;
+
+    typedef enum
+    {
+        MC_DIR_SAT_ID_MCBIST_0 = 0x3,
+        MC_DIR_SAT_ID_MCBIST_1 = 0x4,
+        MC_DIR_SAT_ID_MCBIST_2 = 0x5,
+        MC_DIR_SAT_ID_MCBIST_3 = 0x6
+    } p9_mc_dir1_sat_id_t;
+
+    typedef enum
+    {
+        MC_IND_SAT_ID = 0x0
+    } p9_mc_ind_sat_id_t;
+
+    /// P9 OB chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_ob_top.vhdl
+    typedef enum
+    {
+        OB_PERV_RING_ID = 0x1,      ///< PERV
+        OB_PBIOA_0_RING_ID = 0x2,   ///< PBIOA_0
+        OB_IOO_0_RING_ID = 0x3      ///< IOO_0
+    } p9_ob_ring_id_t;
+
+    typedef enum
+    {
+        OB_PB_SAT_ID = 0x0
+    } p9_ob_pb_sat_id_t;
+
+    typedef enum
+    {
+        OB_IOO_SAT_ID = 0x0,
+        OB_PPE_SAT_ID = 0x1
+    } p9_ob_ioo_sat_id_t;
+
+    /// P9 PCIe chiplet SCOM ring ID enumeration
+    /// source: tpc_p9_pci[012]_top.vhdl
+    typedef enum
+    {
+        PCI_PERV_RING_ID = 0x1,      ///< TRA
+        PCI_PE_0_RING_ID = 0x2,      ///< PE_0
+        PCI_IOPCI_0_RING_ID = 0x3    ///< IOPCI_0
+    } p9_pci_ring_id_t;
+
+
+    /// P9 SCOM address class
+    class p9_scom_addr
+    {
+
+        public:
+            /// @brief Construct a SCOM address object
+            /// @param[in] i_addr 64-bit raw SCOM address
+            p9_scom_addr(const uint64_t i_addr)
+                : iv_addr(i_addr)
+            {
+            }
+
+            /// @brief Set full/raw SCOM address
+            /// @param[in] i_addr 64-bit SCOM address
+            /// @retval none
+            inline void set_addr(const uint64_t i_addr)
+            {
+                iv_addr = i_addr;
+                return;
+            }
+
+            /// @brief Retrieve full/raw SCOM address
+            /// @retval uint64_t 64-bit SCOM address
+            inline uint64_t get_addr() const
+            {
+                return (iv_addr);
+            }
+
+            /// @brief Determine if SCOM address is direct-form
+            /// @retval bool True if SCOM address is direct-form, false otherwise
+            inline bool is_direct() const
+            {
+                return (((iv_addr >> 63) & 0x1) == 0x0);
+            }
+
+            /// @brief Determine if SCOM address is indirect-form
+            /// @retval bool True if SCOM address is indirect-form, false otherwise
+            inline bool is_indirect() const
+            {
+                return (!is_direct());
+            }
+
+            /// @brief Determine if SCOM address is unicast
+            /// @retval bool True if SCOM address is unicast, false otherwise
+            inline bool is_unicast() const
+            {
+                return (!(is_multicast()));
+            }
+
+            /// @brief Determine if SCOM address is multicast
+            /// @retval bool True if SCOM address is multicast, false otherwise
+            inline bool is_multicast() const
+            {
+                return (((iv_addr >> 30) & 0x1) == 0x1);
+            }
+
+            /// @brief Extract pervasive chiplet ID from SCOM address
+            /// @retval uint8_t Pervasive chiplet ID value
+            inline uint8_t get_chiplet_id() const
+            {
+                return ((iv_addr >> 24) & 0x3F);
+            }
+
+            /// @brief Modify SCOM address, update pervasive chiplet ID
+            /// @param[in] i_chiplet_id Chiplet ID value to write
+            /// @retval none
+            inline void set_chiplet_id(const uint8_t i_chiplet_id)
+            {
+                iv_addr &= 0xFFFFFFFFC0FFFFFFULL;
+                iv_addr |= ((i_chiplet_id & 0x3F) << 24);
+                return;
+            }
+
+            /// @brief Extract port field from SCOM address
+            /// @retval uint8_t Port field value
+            inline uint8_t get_port() const
+            {
+                return ((iv_addr >> 16) & 0xF);
+            }
+
+            /// @brief Extract ring field from SCOM address
+            /// @retval uint8_t Ring field value
+            inline uint8_t get_ring() const
+            {
+                return ((iv_addr >> 10) & 0xF);
+            }
+
+            /// @brief Modify SCOM address, update ring field value
+            /// @param[in] i_ring Ring field value to write
+            /// @retval none
+            inline void set_ring(const uint8_t i_ring)
+            {
+                iv_addr &= 0xFFFFFFFFFFFFC3FFULL;
+                iv_addr |= ((i_ring & 0xF) << 10);
+                return;
+            }
+
+            /// @brief Extract satellite ID field from SCOM address
+            /// @retval uint8_t Satellite ID field value
+            inline uint8_t get_sat_id() const
+            {
+                return ((iv_addr >> 6) & 0xF);
+            }
+
+            /// @brief Modify SCOM address, update satellite ID field
+            /// @param[in] i_sat_id Satellite ID value to write
+            /// @retval none
+            inline void set_sat_id(const uint8_t i_sat_id)
+            {
+                iv_addr &= 0xFFFFFFFFFFFFFC3FULL;
+                iv_addr |= ((i_sat_id & 0xF) << 6);
+                return;
+            }
+
+            /// @brief Extract satellite register offset field from SCOM address
+            /// @retval uint8_t Satellite register offset field value
+            inline uint8_t get_sat_offset() const
+            {
+                return (iv_addr & 0x3F);
+            }
+
+            /// @brief Modify SCOM address, update satellite offset field
+            /// @param[in] i_sat_offset Satellite offset value to write
+            /// @retval none
+            inline void set_sat_offset(const uint8_t i_sat_offset)
+            {
+                iv_addr &= 0xFFFFFFFFFFFFFFC0ULL;
+                iv_addr |= (i_sat_offset & 0x3F);
+                return;
+            }
+
+            /// @brief Determine if SCOM address is valid/well-formed
+            /// @retval bool True if SCOM address is valid, false otherwise
+            inline bool is_valid() const
+            {
+                if (iv_addr & 0x0000000000F0C000ULL)
+                {
+                    return false;
+                }
+
+                return true;
+            }
+
+        private:
+            uint64_t iv_addr;   ///< 64-bit raw SCOM address
+    };
+
+} // extern "C"
+
+#endif /* P9_SCOM_ADDR_H */
diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C
new file mode 100644
index 000000000..1b7eeb612
--- /dev/null
+++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C
@@ -0,0 +1,396 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: systems/power9/procedures/p9_scominfo.C $                     */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_scominfo.C
+/// @brief P9 chip unit SCOM address platform translation code
+///
+/// HWP HWP Owner: jmcgill@us.ibm.com
+/// HWP FW Owner: dcrowell@us.ibm.com
+/// HWP Team: Infrastructure
+/// HWP Level: 1
+/// HWP Consumed by: FSP/HB
+///
+
+// includes
+#include "p9_scominfo.H"
+#include "p9_scom_addr.H"
+
+#define P9_SCOMINFO_C
+
+extern "C"
+{
+    uint64_t p9_scominfo_createChipUnitScomAddr(const p9ChipUnits_t i_p9CU, const uint8_t i_chipUnitNum,
+            const uint64_t i_scomAddr, const uint32_t i_mode)
+    {
+        p9_scom_addr l_scom(i_scomAddr);
+        (void) i_mode;
+
+        switch (i_p9CU)
+        {
+            case PU_PERV_CHIPUNIT:
+                l_scom.set_chiplet_id(i_chipUnitNum);
+                break;
+
+            case PU_C_CHIPUNIT:
+                l_scom.set_chiplet_id(EC00_CHIPLET_ID + i_chipUnitNum);
+                break;
+
+            case PU_EX_CHIPUNIT:
+                if (l_scom.get_chiplet_id() == EP00_CHIPLET_ID)
+                {
+                    l_scom.set_chiplet_id(EP00_CHIPLET_ID + (i_chipUnitNum / 2));
+                    l_scom.set_ring(l_scom.get_ring() + (i_chipUnitNum % 2));
+                }
+                else
+                {
+                    l_scom.set_chiplet_id(l_scom.get_chiplet_id() + (i_chipUnitNum * 2));
+                }
+
+                break;
+
+            case PU_EQ_CHIPUNIT:
+                l_scom.set_chiplet_id(EP00_CHIPLET_ID + i_chipUnitNum);
+                break;
+
+            case PU_CAPP_CHIPUNIT:
+                l_scom.set_chiplet_id(N0_CHIPLET_ID + (i_chipUnitNum * 2));
+                break;
+
+            case PU_MCS_CHIPUNIT:
+                l_scom.set_chiplet_id(N3_CHIPLET_ID - (2 * (i_chipUnitNum / 2)));
+                l_scom.set_sat_id(2 * (i_chipUnitNum % 2));
+                break;
+
+            case PU_MCBIST_CHIPUNIT:
+                l_scom.set_chiplet_id(MC01_CHIPLET_ID + i_chipUnitNum);
+                break;
+
+            case PU_MCA_CHIPUNIT:
+                l_scom.set_chiplet_id(MC01_CHIPLET_ID + (i_chipUnitNum / 4));
+
+                if (l_scom.get_ring() == MC_MC01_0_RING_ID)
+                {
+                    // mc
+                    l_scom.set_sat_id(l_scom.get_sat_id() + (i_chipUnitNum % 4));
+                }
+                else
+                {
+                    // iomc
+                    l_scom.set_ring(MC_IOM01_0_RING_ID + (i_chipUnitNum % 4));
+                }
+
+                break;
+
+            case PU_NVBUS_CHIPUNIT:
+                l_scom.set_ring(4 + (i_chipUnitNum / 4));
+                l_scom.set_sat_id(((i_chipUnitNum == 2) || (i_chipUnitNum == 3)) ? 7 : 3);
+                l_scom.set_sat_offset(l_scom.get_sat_offset() + (32 * (i_chipUnitNum % 2)));
+                break;
+
+            case PU_PEC_CHIPUNIT:
+                if (l_scom.get_chiplet_id() == N2_CHIPLET_ID)
+                {
+                    // nest
+                    l_scom.set_ring(N2_PCIS0_0_RING_ID + i_chipUnitNum);
+                }
+                else
+                {
+                    // iopci / pci
+                    l_scom.set_chiplet_id(PCI0_CHIPLET_ID + i_chipUnitNum);
+                }
+
+                break;
+
+            case PU_PHB_CHIPUNIT:
+                if (l_scom.get_chiplet_id() == N2_CHIPLET_ID)
+                {
+                    // nest
+                    if (i_chipUnitNum != 0)
+                    {
+                        l_scom.set_ring(N2_PCIS0_0_RING_ID + (i_chipUnitNum / 3) + 1);
+                        l_scom.set_sat_id(i_chipUnitNum + 2 -
+                                          (l_scom.get_ring() - N2_PCIS0_0_RING_ID));
+                    }
+                }
+                else
+                {
+                    // pci
+                    if (i_chipUnitNum != 0)
+                    {
+                        l_scom.set_chiplet_id(PCI0_CHIPLET_ID + (i_chipUnitNum / 3) + 1);
+                        l_scom.set_sat_id(i_chipUnitNum + 2 -
+                                          (l_scom.get_chiplet_id() - PCI0_CHIPLET_ID));
+                    }
+                }
+
+                break;
+
+            case PU_OBUS_CHIPUNIT:
+                l_scom.set_chiplet_id(OB0_CHIPLET_ID + i_chipUnitNum);
+                break;
+
+            case PU_XBUS_CHIPUNIT:
+                l_scom.set_ring(l_scom.get_ring() + i_chipUnitNum);
+                break;
+
+            default:
+                break;
+        }
+
+        return l_scom.get_addr();
+    }
+
+
+    uint32_t p9_scominfo_isChipUnitScom(const uint64_t i_scomAddr, bool& o_chipUnitRelated,
+                                        std::vector<p9_chipUnitPairing_t>& o_chipUnitPairing, const uint32_t i_mode)
+    {
+        p9_scom_addr l_scom(i_scomAddr);
+        o_chipUnitRelated = false;
+        (void) i_mode;
+
+        uint8_t l_chiplet_id = l_scom.get_chiplet_id();
+        uint8_t l_port = l_scom.get_port();
+        uint8_t l_ring = l_scom.get_ring();
+        uint8_t l_sat_id = l_scom.get_sat_id();
+        uint8_t l_sat_offset = l_scom.get_sat_offset();
+
+        if (l_scom.is_unicast())
+        {
+            // common 'pervasive' registers associated with each pervasive chiplet type
+            // permit addressing by PERV target type (for all pervasive chiplet instances)
+            // or by C/EX/EQ target types (by their associated pervasive chiplet instances)
+            if (((l_port == GPREG_PORT_ID) ||
+                 ((l_port >= CME_PORT_ID) && (l_port <= CPM_PORT_ID)) ||
+                 (l_port == PCBSLV_PORT_ID)))
+            {
+                o_chipUnitRelated = true;
+                // PU_PERV_CHIPUNIT
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PERV_CHIPUNIT,
+                                            l_chiplet_id));
+
+                // PU_C_CHIPUNIT / PU_EX_CHIPUNIT
+                if ((l_chiplet_id >= EC00_CHIPLET_ID) && (l_chiplet_id <= EC23_CHIPLET_ID))
+                {
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_C_CHIPUNIT,
+                                                l_chiplet_id - EC00_CHIPLET_ID));
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_EX_CHIPUNIT,
+                                                (l_chiplet_id - EC00_CHIPLET_ID) / 2));
+                }
+
+                // PU_EQ_CHIPUNIT
+                if ((l_chiplet_id >= EP00_CHIPLET_ID) && (l_chiplet_id <= EP05_CHIPLET_ID))
+                {
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_EQ_CHIPUNIT,
+                                                l_chiplet_id - EP00_CHIPLET_ID));
+                }
+            }
+
+            // core registers which can be addressed by either C/EX target types
+            if (((l_chiplet_id >= EC00_CHIPLET_ID) && (l_chiplet_id <= EC23_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                ((l_ring >= EC_PERV_RING_ID) && (l_ring <= EC_PC_3_RING_ID)))
+            {
+                o_chipUnitRelated = true;
+                // PU_C_CHIPUNIT
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_C_CHIPUNIT,
+                                            l_chiplet_id - EC00_CHIPLET_ID));
+                // PU_EX_CHIPUNIT
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_EX_CHIPUNIT,
+                                            (l_chiplet_id - EC00_CHIPLET_ID) / 2));
+            }
+
+            // quad registers which can be addressed by either EQ/EX target types
+            if (((l_chiplet_id >= EP00_CHIPLET_ID) && (l_chiplet_id <= EP05_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                (((l_ring >= EQ_PERV_RING_ID)  && (l_ring <= EQ_L3_1_RING_ID)) ||
+                 ((l_ring >= EQ_CME_0_RING_ID) && (l_ring <= EQ_L2_1_TRA_RING_ID))))
+            {
+                o_chipUnitRelated = true;
+                // PU_EQ_CHIPUNIT
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_EQ_CHIPUNIT,
+                                            l_chiplet_id - EP00_CHIPLET_ID));
+
+                // PU_EX_CHIPUNIT
+                if ((l_ring == EQ_L2_0_RING_ID)  || (l_ring == EQ_NC_0_RING_ID) || (l_ring == EQ_L3_0_RING_ID) ||
+                    (l_ring == EQ_CME_0_RING_ID) || (l_ring == EQ_L2_0_TRA_RING_ID))
+                {
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_EX_CHIPUNIT,
+                                                (l_chiplet_id - EP00_CHIPLET_ID) * 2));
+                }
+                // PU_EX_CHIPUNIT
+                else if ((l_ring == EQ_L2_1_RING_ID)  || (l_ring == EQ_NC_1_RING_ID) || (l_ring == EQ_L3_1_RING_ID) ||
+                         (l_ring == EQ_CME_1_RING_ID) || (l_ring == EQ_L2_1_TRA_RING_ID))
+                {
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_EX_CHIPUNIT,
+                                                ((l_chiplet_id - EP00_CHIPLET_ID) * 2) + 1));
+                }
+            }
+
+            // PU_CAPP_CHIPUNIT
+            if ((((l_chiplet_id == N0_CHIPLET_ID) && (l_ring == N0_CXA0_0_RING_ID)) ||
+                 ((l_chiplet_id == N2_CHIPLET_ID) && (l_ring == N2_CXA1_0_RING_ID))) &&
+                (l_port == UNIT_PORT_ID))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_CAPP_CHIPUNIT,
+                                            (l_chiplet_id / 2) - 1));
+            }
+
+            // PU_MCS_CHIPUNIT (nest)
+            if (((l_chiplet_id == N3_CHIPLET_ID) || (l_chiplet_id == N1_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                (l_ring == N3_MC01_0_RING_ID) &&
+                ((l_sat_id == MC_DIR_SAT_ID_PBI_01) || (l_sat_id == MC_DIR_SAT_ID_PBI_23)))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCS_CHIPUNIT,
+                                            ((l_chiplet_id == N3_CHIPLET_ID) ? (0) : (2)) +
+                                            (l_sat_id / 2)));
+            }
+
+            // PU_MCBIST_CHIPUNIT (mc)
+            if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                (l_ring == MC_MC01_1_RING_ID) &&
+                ((l_sat_id >= MC_DIR_SAT_ID_MCBIST_0) && (l_sat_id <= MC_DIR_SAT_ID_MCBIST_3)))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCBIST_CHIPUNIT,
+                                            l_chiplet_id - MC01_CHIPLET_ID));
+            }
+
+            // PU_MCA_CHIPUNIT (mc)
+            if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                (l_ring == MC_MC01_0_RING_ID) &&
+                ((l_sat_id >= MC_DIR_SAT_ID_SRQ_0) && (l_sat_id <= MC_DIR_SAT_ID_ECC64_3)))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
+                                            (4 * (l_chiplet_id - MC01_CHIPLET_ID)) +
+                                            (l_sat_id % 4)));
+            }
+
+            // PU_MCA_CHIPUNIT (iomc)
+            if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                ((l_ring >= MC_IOM01_0_RING_ID) && (l_ring <= MC_IOM23_1_RING_ID)) &&
+                (l_sat_id == MC_IND_SAT_ID))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
+                                            (4 * (l_chiplet_id - MC01_CHIPLET_ID)) +
+                                            (l_ring - MC_IOM01_0_RING_ID)));
+            }
+
+            // PU_NVBUS_CHIPUNIT
+            if ((l_chiplet_id == N3_CHIPLET_ID) &&
+                (l_port == UNIT_PORT_ID) &&
+                (((l_ring == N3_NPU_0_RING_ID) && ((l_sat_id == 3) || (l_sat_id == 7))) ||
+                 ((l_ring == N3_NPU_1_RING_ID) && (l_sat_id == 3))))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NVBUS_CHIPUNIT,
+                                            (4 * (l_ring - N3_NPU_0_RING_ID)) +
+                                            (2 * (l_sat_id / 7)) +
+                                            (l_sat_offset / 32)));
+            }
+
+            // PU_PEC_CHIPUNIT (nest)
+            if ((l_chiplet_id == N2_CHIPLET_ID) &&
+                (l_port == UNIT_PORT_ID) &&
+                ((l_ring >= N2_PCIS0_0_RING_ID) && (l_ring <= N2_PCIS2_0_RING_ID)) &&
+                (l_sat_id == PEC_SAT_ID))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PEC_CHIPUNIT,
+                                            (l_ring - N2_PCIS0_0_RING_ID)));
+            }
+
+            // PU_PEC_CHIPUNIT (iopci/pci)
+            // source: iop_scom_cntl_rlm_mac.vhdl
+            if (((l_chiplet_id >= PCI0_CHIPLET_ID) && (l_chiplet_id <= PCI2_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                ((l_ring == PCI_IOPCI_0_RING_ID) || (l_ring == PCI_PE_0_RING_ID)) &&
+                (l_sat_id == PEC_SAT_ID))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PEC_CHIPUNIT,
+                                            (l_chiplet_id - PCI0_CHIPLET_ID)));
+            }
+
+            // PU_PHB_CHIPUNIT (nest)
+            if ((l_chiplet_id == N2_CHIPLET_ID) &&
+                (l_port == UNIT_PORT_ID) &&
+                ((l_ring >= N2_PCIS0_0_RING_ID) && (l_ring <= N2_PCIS2_0_RING_ID)) &&
+                (((l_ring - l_sat_id) >= 2) && ((l_ring - l_sat_id) < l_ring)))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PHB_CHIPUNIT,
+                                            ((l_ring - N2_PCIS0_0_RING_ID) ?
+                                             (((l_ring - N2_PCIS0_0_RING_ID) * 2) - 1) :
+                                             (0)) +
+                                            (l_sat_id - 1)));
+            }
+
+            // PU_PHB_CHIPUNIT (pci)
+            if (((l_chiplet_id >= PCI0_CHIPLET_ID) && (l_chiplet_id <= PCI2_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                (l_ring == PCI_PE_0_RING_ID) &&
+                (((l_sat_id >= 1) && (l_sat_id <= (l_chiplet_id - PCI0_CHIPLET_ID + 1))) || // aib_stack
+                 ((l_sat_id >= 4) && (l_sat_id <= (l_chiplet_id - PCI0_CHIPLET_ID + 4)))))  // pbcq_etu
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PHB_CHIPUNIT,
+                                            ((l_chiplet_id - PCI0_CHIPLET_ID) ?
+                                             (((l_chiplet_id - PCI0_CHIPLET_ID) * 2) - 1) :
+                                             (0)) +
+                                            l_sat_id -
+                                            ((l_sat_id >= 4) ? (4) : (1))));
+            }
+
+            // PU_OBUS_CHIPUNIT
+            if (((l_chiplet_id >= OB0_CHIPLET_ID) && (l_chiplet_id <= OB3_CHIPLET_ID)) &&
+                (l_port == UNIT_PORT_ID) &&
+                (((l_ring == OB_PBIOA_0_RING_ID) && (l_sat_id == OB_PB_SAT_ID)) ||
+                 ((l_ring == OB_IOO_0_RING_ID) && ((l_sat_id == OB_IOO_SAT_ID) || (l_sat_id == OB_PPE_SAT_ID)))))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_OBUS_CHIPUNIT,
+                                            (l_chiplet_id - OB0_CHIPLET_ID)));
+            }
+
+            // PU_XBUS_CHIPUNIT
+            if ((l_chiplet_id == XB_CHIPLET_ID) &&
+                (l_port == UNIT_PORT_ID) &&
+                (((l_ring >= XB_IOX_0_RING_ID) && (l_ring <= XB_IOX_2_RING_ID) && (l_sat_id == XB_IOF_SAT_ID)) ||
+                 ((l_ring >= XB_PBIOX_0_RING_ID) && (l_ring <= XB_PBIOX_2_RING_ID) && (l_sat_id == XB_PB_SAT_ID))))
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_XBUS_CHIPUNIT,
+                                            l_ring % 3));
+            }
+        }
+
+        return (!l_scom.is_valid());
+    }
+
+} // extern "C"
+
+#undef P9_SCOMINFO_C
diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.H b/src/import/chips/p9/common/scominfo/p9_scominfo.H
new file mode 100644
index 000000000..0262bffe5
--- /dev/null
+++ b/src/import/chips/p9/common/scominfo/p9_scominfo.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: systems/power9/procedures/p9_scominfo.H $                     */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_scominfo.H
+/// @brief P9 chip unit SCOM address platform translation code
+///
+/// HWP HWP Owner: jmcgill@us.ibm.com
+/// HWP FW Owner: dcrowell@us.ibm.com
+/// HWP Team: Infrastructure
+/// HWP Level: 1
+/// HWP Consumed by: FSP/HB
+///
+
+#ifndef P9_SCOMINFO_H
+#define P9_SCOMINFO_H
+
+// includes
+#include <stdint.h>
+#include <vector>
+#include "p9_cu.H"
+
+extern "C"
+{
+    /// @brief Creates the actual SCOM address based on the chip unit type, instance, and the input SCOM address (relative to chip unit instance 0)
+    /// @param[in] i_p9CU Enumeration of the chip unit type
+    /// @param[in] i_chipUnitNum Instance number of the chip unit
+    /// @param[in] i_scomAddr The input SCOM address associated with the chip unit type
+    /// @param[in] i_mode Used for special purposes, default to 0
+    /// @retval uint64_t Actual SCOM address for the chip unit instance passed in
+    uint64_t p9_scominfo_createChipUnitScomAddr(const p9ChipUnits_t i_p9CU, const uint8_t i_chipUnitNum,
+            const uint64_t i_scomAddr, const uint32_t i_mode = 0);
+
+    /// @brief Determine if the provided SCOM address correlates to any chip units (if so creates a list of chipUnitPairing structures which correspond)
+    /// @param[in] i_scomAddr SCOM address to be tested
+    /// @param[out] o_chipUnitRelated Returns true if SCOM address is associated with any chip units
+    /// @param[out] o_chipUnitPairing Collection of chipUnitPairing enums
+    /// @param[in] i_mode Used for special purposes, default to 0
+    /// @retval uint32_t Return non-zero for error
+    uint32_t p9_scominfo_isChipUnitScom(const uint64_t i_scomAddr, bool& o_chipUnitRelated,
+                                        std::vector<p9_chipUnitPairing_t>& o_chipUnitPairing, const uint32_t i_mode = 0);
+
+} // extern "C"
+
+#endif /* P9_SCOMINFO_H */