NPU SCOM translation support for Axone

Change-Id: I8e4d883ea578c03b468e113e66bd834adf52ba5c
RTC: 208523
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77575
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Benjamen G. Tyner <ben.tyner@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77638
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

3 files changed, 96 insertions, 2 deletions

diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H
index 620e072a9..180828620 100644
--- a/src/import/chips/p9/common/scominfo/p9_cu.H
+++ b/src/import/chips/p9/common/scominfo/p9_cu.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -68,7 +68,8 @@ extern "C"
         PU_PPE_CHIPUNIT,     ///< PPE
         PU_SBE_CHIPUNIT,     ///< SBE
         PU_CAPP_CHIPUNIT,    ///< CAPP
-        PU_MC_CHIPUNIT,    ///< mc
+        PU_MC_CHIPUNIT,      ///< mc
+        PU_NPU_CHIPUNIT,     ///< NPU
         NONE,                ///< None/Invalid
     } p9ChipUnits_t;
 
diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
index 513cf0db6..b3d1186c0 100644
--- a/src/import/chips/p9/common/scominfo/p9_scom_addr.H
+++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
@@ -452,6 +452,13 @@ extern "C"
         P9A_MC_OMI2_FRST_LANE = 0x10,     ///< First lane of OMI % 3 = 2
     } p9a_mc_lane_t;
 
+    typedef enum
+    {
+        P9A_NPU_2_RING_ID     = 0x7,
+        P9A_NPU_2_FIR_RING_ID = 0x8,
+        P9A_NPU_0_FIR_RING_ID = 0xF,
+    } p9a_npu_ring_id_t;
+
 //        8             7             6             5             4             3          2         1
 //
 //  |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31|
diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C
index 0039625ca..0426537d4 100644
--- a/src/import/chips/p9/common/scominfo/p9_scominfo.C
+++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C
@@ -646,6 +646,61 @@ extern "C"
 
                     break;
 
+                case PU_NPU_CHIPUNIT:
+
+                    // NPU0 and NPU1 exist on the N3 chiplet, NPU2 exists on the N1 chiplet instead
+                    l_chiplet_id = ( 2 == i_chipUnitNum ) ? N1_CHIPLET_ID : N3_CHIPLET_ID ;
+                    l_scom.set_chiplet_id( l_chiplet_id );
+
+                    // Covers the following addresses:
+                    // NPU0: 05011000 to 050113FF
+                    // NPU1: 05011400 to 050117FF
+                    // NPU2: 03011C00 to 03011FFF
+                    if ( N3_NPU_0_RING_ID == l_ring )
+                    {
+                        // NPU0/NPU1
+                        if ( N3_CHIPLET_ID == l_chiplet_id )
+                        {
+                            l_scom.set_ring( N3_NPU_0_RING_ID + i_chipUnitNum );
+                        }
+                        // NPU2
+                        else if ( N1_CHIPLET_ID == l_chiplet_id )
+                        {
+                            l_scom.set_ring( P9A_NPU_2_RING_ID );
+                        }
+                        else
+                        {
+                            l_scom.set_addr( FAILED_TRANSLATION );
+                        }
+                    }
+                    // Covers the following addresses:
+                    // NPU0: 05013C00 to 05013C8F
+                    // NPU1: 05013CC0 to 05013D4F
+                    // NPU2: 03012000 to 0301208F
+                    else if ( P9A_NPU_0_FIR_RING_ID == l_ring )
+                    {
+                        // NPU0/NPU1
+                        if ( N3_CHIPLET_ID == l_chiplet_id )
+                        {
+                            l_scom.set_sat_id( l_sat_id + (3 * i_chipUnitNum) );
+                        }
+                        // NPU2
+                        else if ( N1_CHIPLET_ID == l_chiplet_id )
+                        {
+                            l_scom.set_ring( P9A_NPU_2_FIR_RING_ID );
+                        }
+                        else
+                        {
+                            l_scom.set_addr( FAILED_TRANSLATION );
+                        }
+                    }
+                    else
+                    {
+                        l_scom.set_addr( FAILED_TRANSLATION );
+                    }
+
+                    break;
+
                 default:
                     l_scom.set_addr(FAILED_TRANSLATION);
                     break;
@@ -1498,6 +1553,37 @@ extern "C"
                 o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT,
                                             (l_chiplet_id - OB0_CHIPLET_ID) + PPE_IO_OB0_CHIPUNIT_NUM));
             }
+
+            // PU_NPU_CHIPUNIT
+            // npu: 0..1
+            if ( (l_port == UNIT_PORT_ID) &&
+                 (l_chiplet_id == N3_CHIPLET_ID) &&
+                 (N3_NPU_0_RING_ID <= l_ring && l_ring <= N3_NPU_1_RING_ID) )
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT,
+                                            (l_ring - N3_NPU_0_RING_ID)));
+            }
+
+            if ( (l_port == UNIT_PORT_ID) &&
+                 (l_chiplet_id == N3_CHIPLET_ID) &&
+                 (l_ring == P9A_NPU_0_FIR_RING_ID) )
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT,
+                                            (l_sat_id / 3)));
+            }
+
+            // PU_NPU_CHIPUNIT
+            // npu: 2
+            if ( (l_port == UNIT_PORT_ID) &&
+                 (l_chiplet_id == N1_CHIPLET_ID) &&
+                 (l_ring == P9A_NPU_2_RING_ID || l_ring == P9A_NPU_2_FIR_RING_ID) )
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT, 2));
+            }
+
         }
 
         return (!l_scom.is_valid());