WOF Enablement in PGPE

    -Full functionality for OCC Start/Stop, Set PMCR, Clip Updt
    -New code structure for PGPE(actuate/process thread, etc)
    -Update CME code as per the new Doorbell0
    -Added place holders for SGPE-PGPE IPCs
    -Place holders for Error Interrupts like OCB_Error, XSTOP
    -Added code to correctly account for VRM transition delays

Change-Id: I301b14304677e2ed0130f1c3479d523dcb931293
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34156
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34157
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 19 insertions, 14 deletions

diff --git a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
index a19c96c46..d5106c0db 100644
--- a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
+++ b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -41,9 +41,6 @@
 extern "C" {
 #endif
 
-// Maximum Number of Quads supported
-#define MAX_QUADS 6
-
 
 //---------------
 // IPC from 405
@@ -62,11 +59,19 @@ enum MESSAGE_ID_IPI2HI
 //
 // Return Codes
 //
-#define PGPE_RC_SUCCESS                 0x01
-#define PGPE_WOF_RC_NOT_ENABLED         0x10
+//\todo
+//Get feedback from Martha and Greg on these return codes
+//
+#define PGPE_RC_SUCCESS                         0x01
+#define PGPE_WOF_RC_NOT_ENABLED                 0x10
+#define PGPE_RC_PSTATES_DISABLED                0x11
+#define PGPE_RC_REQ_PSTATE_ALREADY_STARTED      0x12
+#define PGPE_RC_REQ_PSTATE_ALREADY_SUSPENDED    0x13
+#define PGPE_RC_OCC_NOT_PMCR_OWNER              0x14
 // Active quad mismatch with requested active quads.  PGPE did not switch
 // to using the new VFRT.  The original VFRT is still being used.
 #define PGPE_WOF_RC_VFRT_QUAD_MISMATCH  0x20
+#define PGPE_RC_REQ_WHILE_PENDING_ACK   0x21
 
 //
 // PMCR Owner
@@ -74,7 +79,8 @@ enum MESSAGE_ID_IPI2HI
 typedef enum
 {
     PMCR_OWNER_HOST         = 0,
-    PMCR_OWNER_OCC          = 1
+    PMCR_OWNER_OCC          = 1,
+    PMCR_OWNER_CHAR         = 2
 } PMCR_OWNER;
 
 
@@ -88,14 +94,14 @@ typedef struct ipcmsg_base
 // Start Suspend Actions
 //
 #define PGPE_ACTION_PSTATE_START   0
-#define PGPE_ACTION_PSTATE_SUSPEND 1
+#define PGPE_ACTION_PSTATE_STOP    1
 
-typedef struct ipcmsg_start_suspend
+typedef struct ipcmsg_start_stop
 {
     ipcmsg_base_t   msg_cb;
     uint8_t         action;
     PMCR_OWNER      pmcr_owner;
-} ipcmsg_start_suspend_t;
+} ipcmsg_start_stop_t;
 
 
 typedef struct ipcmsg_clip_update
@@ -269,9 +275,9 @@ typedef union quad_state0
         uint64_t quad1_pstate             : 8;  // Pstate of Quad 1; 0xFF indicates EQ is off
         uint64_t quad2_pstate             : 8;  // Pstate of Quad 2; 0xFF indicates EQ is off
         uint64_t quad3_pstate             : 8;  // Pstate of Quad 3; 0xFF indicates EQ is off
+        uint64_t core_poweron_state       : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15
         uint64_t ivrm_state               : 4;  // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3
         uint64_t ivrm_state_rsvd          : 4;
-        uint64_t core_poweron_state       : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15
         uint64_t external_vrm_setpoint    : 8;  // set point in mV
     } fields;
 } quad_state0_t;
@@ -288,12 +294,11 @@ typedef union quad_state1
     {
         uint64_t quad4_pstate             : 8;  // Pstate of Quad 4; 0xFF indicates EQ is off
         uint64_t quad5_pstate             : 8;  // Pstate of Quad 5; 0xFF indicates EQ is off
-        uint64_t requested_active_quad    : 6;  // Pstate of Quad 5; 0xFF indicates EQ is off
-        uint64_t quad_pstate_rsvd         : 10;
+        uint64_t reserved                 : 16;
         uint64_t ivrm_state               : 2;  // ivrm state: bit vector 0:quad4, 1:quad5
         uint64_t ivrm_state_rsvd          : 6;
         uint64_t core_poweron_state       : 8;  // bit vector: 0:core16, 1:core17, ..., 7:core23
-        uint64_t core_poweron_state_rsvd  : 8;
+        uint64_t requested_active_quad    : 8;
         uint64_t external_vrm_setpoint    : 8;  // set point in mV
     } fields;
 } quad_state1_t;