diff options
| author | Ben Gass <bgass@us.ibm.com> | 2016-02-19 18:30:34 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-03-02 13:48:12 -0500 |
| commit | f56d1d03148649551ece55bc1743f1d1762a119f (patch) | |
| tree | 97d47bbfbb8c33c241fce0e490fd1ca8684ea1aa /src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H | |
| parent | dfa46b0cd43ac82181f29ce9bd76d21d6dc681e6 (diff) | |
| download | talos-hostboot-f56d1d03148649551ece55bc1743f1d1762a119f.tar.gz talos-hostboot-f56d1d03148649551ece55bc1743f1d1762a119f.zip | |
New scom address constants generated from e9034
Change-Id: Ibd2e7c8278af9554c6379e65ab8b590288f133dc
Original-Change-Id: I52e35aa1c91f215730dac2ae0b8d9f42332c49e0
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24545
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21592
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H | 2350 |
1 files changed, 1653 insertions, 697 deletions
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H index 1a028a101..88e06aa0c 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H @@ -3377,62 +3377,85 @@ REG64_FLD( MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP , 6 , SH_UN REG64_FLD( MCBIST_CCS_STATQ_FAIL_RCD , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_FAIL_RCD ); -REG64_FLD( MCA_CERR0_RECR_PE , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_RECR_PE , 10 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_RECR_PE ); -REG64_FLD( MCA_CERR0_MSR_PE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_MSR_PE , 12 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_MSR_PE ); -REG64_FLD( MCA_CERR0_EICR_PE , 13 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_EICR_PE , 13 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_EICR_PE ); -REG64_FLD( MCA_CERR0_HWMSX_PE , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_HWMSX_PE , 16 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_HWMSX_PE ); -REG64_FLD( MCA_CERR0_HWMSX_PE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_HWMSX_PE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_HWMSX_PE_LEN ); -REG64_FLD( MCA_CERR0_FWMSX_PE , 24 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_FWMSX_PE , 24 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_FWMSX_PE ); -REG64_FLD( MCA_CERR0_FWMSX_PE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_FWMSX_PE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_FWMSX_PE_LEN ); -REG64_FLD( MCA_CERR0_WECR_PE , 40 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_WECR_PE , 40 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_WECR_PE ); -REG64_FLD( MCA_CERR0_AACR_PE , 41 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_AACR_PE , 41 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_AACR_PE ); -REG64_FLD( MCA_CERR0_AADR_PE , 42 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_AADR_PE , 42 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_AADR_PE ); -REG64_FLD( MCA_CERR0_AAER_PE , 43 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_AAER_PE , 43 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_AAER_PE ); -REG64_FLD( MCA_CERR0_MCBCM_PE , 44 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_MCBCM_PE , 44 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_MCBCM_PE ); -REG64_FLD( MCA_CERR0_WDFCFG_PE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_WDFCFG_PE , 48 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_WDFCFG_PE ); -REG64_FLD( MCA_CERR0_WRTCFG_PE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR0_WRTCFG_PE , 56 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_WRTCFG_PE ); -REG64_FLD( MCA_CERR1_READ_ECC_CONTROL_PARITY_ERROR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_READ_ECC_CONTROL_PARITY_ERROR ); -REG64_FLD( MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR , 1 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_ECC_CTL_AF_PERR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_AF_PERR ); +REG64_FLD( MCA_CERR1_ECC_CTL_RPTR_PERR , 1 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_RPTR_PERR ); +REG64_FLD( MCA_CERR1_ECC_CTL_TCHN_PERR , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_TCHN_PERR ); +REG64_FLD( MCA_CERR1_ECC_CTL_CMPMODE_ERR , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_CMPMODE_ERR ); +REG64_FLD( MCA_CERR1_ECC_CTL_SCH_PERR , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_SCH_PERR ); +REG64_FLD( MCA_CERR1_ECC_CTL_PCTL_PERR , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_PCTL_PERR ); +REG64_FLD( MCA_CERR1_ECC_CTL_TGST_PERR , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_TGST_PERR ); +REG64_FLD( MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR ); -REG64_FLD( MCA_CERR1_READ_ECC_ECCPIPE_PARITY_ERROR , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_READ_ECC_ECCPIPE_PARITY_ERROR ); -REG64_FLD( MCA_CERR1_PHY_PARITY_HOLD_OUT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_0 , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_PARITY_ERROR_0 ); +REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_1 , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_PARITY_ERROR_1 ); +REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_2 , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_PARITY_ERROR_2 ); +REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_3 , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_PARITY_ERROR_3 ); +REG64_FLD( MCA_CERR1_PHY_PARITY_HOLD_OUT , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PHY_PARITY_HOLD_OUT ); -REG64_FLD( MCA_CERR1_WDF_ASYNC_ERROR , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WDF_ASYNC_ERROR , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WDF_ASYNC_ERROR ); -REG64_FLD( MCA_CERR1_WDF_BUFFER_CE , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WDF_BUFFER_CE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WDF_BUFFER_CE ); -REG64_FLD( MCA_CERR1_WDF_BUFFER_UE , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WDF_BUFFER_UE , 18 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WDF_BUFFER_UE ); -REG64_FLD( MCA_CERR1_WDF_BUFFER_SUE , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WDF_BUFFER_SUE , 19 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WDF_BUFFER_SUE ); -REG64_FLD( MCA_CERR1_WRT_BUFFER_CE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WRT_BUFFER_CE , 25 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WRT_BUFFER_CE ); -REG64_FLD( MCA_CERR1_WRT_BUFFER_UE , 18 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WRT_BUFFER_UE , 26 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WRT_BUFFER_UE ); -REG64_FLD( MCA_CERR1_WRT_BUFFER_SUE , 19 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WRT_BUFFER_SUE , 27 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WRT_BUFFER_SUE ); -REG64_FLD( MCA_CERR1_READ_CONTROL_OVERFLOW_ERROR , 24 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_READ_CONTROL_OVERFLOW_ERROR , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_READ_CONTROL_OVERFLOW_ERROR ); -REG64_FLD( MCA_CERR1_WRITE_ECC_DATAPATH_ERROR , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_WRITE_ECC_DATAPATH_ERROR , 40 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WRITE_ECC_DATAPATH_ERROR ); +REG64_FLD( MCBIST_CLKRATIO_RATIO , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RATIO ); +REG64_FLD( MCBIST_CLKRATIO_RATIO_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RATIO_LEN ); + REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_ENABLE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_DBG_ENABLE ); REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01 , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -3530,10 +3553,14 @@ REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE , 41 , SH_UN SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE ); REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN ); -REG64_FLD( MCBIST_DBGCFG3Q_RESERVED_45_47 , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_45_47 ); -REG64_FLD( MCBIST_DBGCFG3Q_RESERVED_45_47_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_45_47_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNT_VALUE ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNT_VALUE_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE , 51 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_TMR_VALUE ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_TMR_VALUE_LEN ); REG64_FLD( MCA_DBGR_ECC_DEBUG_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ECC_DEBUG_ENABLE ); @@ -3598,23 +3625,27 @@ REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15 , 60 , SH_UN REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_12_15_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_DLL_COMPARE_OUT ); REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01 ); @@ -4056,47 +4087,63 @@ REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR12_ADR13 , 54 , SH_U REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR14_ADR15 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DI_ADR14_ADR15 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN ); + SH_ACS_SCOM , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC ); + SH_ACS_SCOM , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN ); + SH_ACS_SCOM , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC ); + SH_ACS_SCOM , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_CAL_ERROR_FINE ); REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_REGS_RXDLL_VREG ); @@ -4118,6 +4165,28 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG , 48 , REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_REGS_RXDLL_VREG_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE_LEN ); + REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0 ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -4138,55 +4207,55 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1 , 48 , SH_UN REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_DETECT_REQ ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_SLAVE_CAL_CKT_POWERDOWN ); + SH_ACS_SCOM , SH_FLD_ADR0_SLAVE_CAL_CKT_POWERDOWN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_VREG_RXCAL_COMP_OUT_META ); + SH_ACS_SCOM , SH_FLD_ADR0_VREG_RXCAL_COMP_OUT_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXCAL_DETECT_DONE_META ); + SH_ACS_SCOM , SH_FLD_ADR0_RXCAL_DETECT_DONE_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXCAL_PD_CAL_LAG_META ); + SH_ACS_SCOM , SH_FLD_ADR0_RXCAL_PD_CAL_LAG_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXCAL_PD_MAIN_LEAD_META ); + SH_ACS_SCOM , SH_FLD_ADR0_RXCAL_PD_MAIN_LEAD_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXCAL_PD_MAIN_LAG_META ); + SH_ACS_SCOM , SH_FLD_ADR0_RXCAL_PD_MAIN_LAG_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_VREG_SLAVE1_COMP_OUT , 61 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_VREG_SLAVE1_COMP_OUT ); + SH_ACS_SCOM , SH_FLD_ADR0_VREG_SLAVE1_COMP_OUT ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_VREG_SLAVE2_COMP_OUT , 62 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_VREG_SLAVE2_COMP_OUT ); + SH_ACS_SCOM , SH_FLD_ADR0_VREG_SLAVE2_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_DETECT_REQ ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_SLAVE_CAL_CKT_POWERDOWN ); + SH_ACS_SCOM , SH_FLD_ADR1_SLAVE_CAL_CKT_POWERDOWN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_VREG_RXCAL_COMP_OUT_META ); + SH_ACS_SCOM , SH_FLD_ADR1_VREG_RXCAL_COMP_OUT_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXCAL_DETECT_DONE_META ); + SH_ACS_SCOM , SH_FLD_ADR1_RXCAL_DETECT_DONE_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXCAL_PD_CAL_LAG_META ); + SH_ACS_SCOM , SH_FLD_ADR1_RXCAL_PD_CAL_LAG_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXCAL_PD_MAIN_LEAD_META ); + SH_ACS_SCOM , SH_FLD_ADR1_RXCAL_PD_MAIN_LEAD_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXCAL_PD_MAIN_LAG_META ); + SH_ACS_SCOM , SH_FLD_ADR1_RXCAL_PD_MAIN_LAG_META ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_VREG_SLAVE1_COMP_OUT , 61 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_VREG_SLAVE1_COMP_OUT ); + SH_ACS_SCOM , SH_FLD_ADR1_VREG_SLAVE1_COMP_OUT ); REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_VREG_SLAVE2_COMP_OUT , 62 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_VREG_SLAVE2_COMP_OUT ); + SH_ACS_SCOM , SH_FLD_ADR1_VREG_SLAVE2_COMP_OUT ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_REGS_RXDLL_EN ); @@ -5038,15 +5107,23 @@ REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16 , 54 , SH_UN SH_FLD_ERR_FSM_DP16 ); REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ERR_FSM_DP16_LEN ); - -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_ERR_STATUS0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PC_ERR_STATUS0 ); -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_ERR_STATUS0_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PC_ERR_STATUS0_LEN ); -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PC_INIT_CAL_ERR ); -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PC_INIT_CAL_ERR_LEN ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DP_DLL_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR_FINE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DP_DLL_CAL_ERROR_FINE ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR_DLL_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR_DLL_CAL_ERROR_FINE ); REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_ERR0_REG_DP16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ERR0_REG_DP16 ); @@ -5225,10 +5302,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UN SH_FLD_01_NIB_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5237,10 +5310,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_U SH_FLD_01_NIB_1_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_1_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5250,10 +5319,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_U SH_FLD_01_NIB_0_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_0_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5262,10 +5327,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UN SH_FLD_01_NIB_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5275,10 +5336,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UN SH_FLD_23_NIB_0_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5287,10 +5344,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_U SH_FLD_23_NIB_1_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5300,10 +5353,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_U SH_FLD_23_NIB_0_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5312,10 +5361,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UN SH_FLD_23_NIB_1_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5325,10 +5370,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UN SH_FLD_4_NIB_0_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_0_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5337,10 +5378,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UN SH_FLD_4_NIB_1_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_1_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5350,10 +5387,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UN SH_FLD_01_NIB_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5362,10 +5395,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_U SH_FLD_01_NIB_1_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_1_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5375,10 +5404,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_U SH_FLD_01_NIB_0_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_0_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5387,10 +5412,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UN SH_FLD_01_NIB_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_NIB_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5400,10 +5421,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UN SH_FLD_23_NIB_0_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5412,10 +5429,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_U SH_FLD_23_NIB_1_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5425,10 +5438,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_U SH_FLD_23_NIB_0_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_0_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5437,10 +5446,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UN SH_FLD_23_NIB_1_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_NIB_1_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5450,10 +5455,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UN SH_FLD_4_NIB_0_2_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_50_52 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_50_52_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_0_2_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5462,10 +5463,6 @@ REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UN SH_FLD_4_NIB_1_3_DQSEL_CAP ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_58_60 ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_RESERVED_58_60_LEN ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_NIB_1_3_DQSEL_RES ); REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5931,95 +5928,115 @@ REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N2 , 62 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_MRS_CMD_N3 ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DLL_COMPARE_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_ADJUST ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_ADJUST_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_CORRECT_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DLL_COMPARE_OUT ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_HS_PROBE_A ); @@ -6291,215 +6308,295 @@ REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR , 58 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_ERROR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FINECAL_2XILSB_DC , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_RXREG_FINECAL_2XILSB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CAL_ERROR_FINE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_HS_DLLMUX_SEL_0_3 ); @@ -6686,6 +6783,116 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER , 48 , S REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SLAVE_VREG_DAC_COARSE_LEN ); + REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -6786,234 +6993,234 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER , 48 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_UPPER_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_VREG_SLAVE_COMP_OUT ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_OVERRIDE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_CAL_PD_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_MAIN_PD_ENABLE , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_MAIN_PD_ENABLE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_DETECT_REQ , 51 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DETECT_REQ ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_SLAVE_CAL_CKT_POWERDOWN , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_SLAVE_CAL_CKT_POWERDOWN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_RXCAL_COMP_OUT_META , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_VREG_RXCAL_COMP_OUT_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_DETECT_DONE_META , 57 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_DETECT_DONE_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_CAL_LAG_META , 58 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_PD_CAL_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LEAD_META , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_PD_MAIN_LEAD_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LAG_META , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXCAL_PD_MAIN_LAG_META ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_SLAVE_COMP_OUT , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_VREG_SLAVE_COMP_OUT ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -17226,185 +17433,665 @@ REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX , 56 , S REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_CTR_SINGLE_RANGE_MAX_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TBD2_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TBD1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD1 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TBD1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TBD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD2 ); -REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TBD2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TBD2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR0 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR0 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR0 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR0 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MAX_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MIN_RANGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_TWO_RANGE_BEST_CASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BIT_STEP_DELTA_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR0 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_STEP_RANGE_EDGE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_NO_INCREASE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_1D_EYE_NOISE_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BAD_BIT_ERR0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MAX_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MIN_RANGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_TWO_RANGE_BEST_CASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BIT_STEP_DELTA_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_STEP_RANGE_EDGE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_NO_INCREASE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_1D_EYE_NOISE_ERR1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BAD_BIT_ERR1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MAX_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MIN_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TWO_RANGE_BEST_CASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_STEP_DELTA_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_STEP_RANGE_EDGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_NO_INCREASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_1D_EYE_NOISE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BAD_BIT_ERR3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MAX_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MIN_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_TWO_RANGE_BEST_CASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_STEP_DELTA_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_STEP_RANGE_EDGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_NO_INCREASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_1D_EYE_NOISE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BAD_BIT_ERR3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MAX_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MIN_RANGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_TWO_RANGE_BEST_CASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BIT_STEP_DELTA_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_STEP_RANGE_EDGE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_NO_INCREASE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_1D_EYE_NOISE_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BAD_BIT_ERR2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MAX_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MIN_RANGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_TWO_RANGE_BEST_CASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BIT_STEP_DELTA_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_STEP_RANGE_EDGE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_NO_INCREASE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_1D_EYE_NOISE_ERR3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BAD_BIT_ERR3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TWO_RANGE_BEST_CASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE_MASK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE_MASK1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE_MASK1 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA_MASK1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE_MASK1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE_MASK1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE_MASK1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT_MASK1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT_MASK1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TWO_RANGE_BEST_CASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE_MASK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE_MASK1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE_MASK1 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA_MASK1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE_MASK1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE_MASK1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE_MASK1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT_MASK1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT_MASK1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TWO_RANGE_BEST_CASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE_MASK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE_MASK1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE_MASK1 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA_MASK1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE_MASK1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE_MASK1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE_MASK1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT_MASK1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT_MASK1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TWO_RANGE_BEST_CASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE_MASK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE_MASK1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE_MASK1 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA_MASK1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE_MASK1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE_MASK1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE_MASK1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT_MASK1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT_MASK1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MAX_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_TWO_RANGE_BEST_CASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BIT_STEP_DELTA ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_STEP_RANGE_EDGE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_INCREASE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_1D_EYE_NOISE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BAD_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE_MASK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MAX_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE_MASK1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_RANGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE_MASK1 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_TWO_RANGE_BEST_CASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA_MASK1 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BIT_STEP_DELTA_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE_MASK1 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_STEP_RANGE_EDGE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE_MASK1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_INCREASE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE_MASK1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_1D_EYE_NOISE_MASK1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT_MASK1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BAD_BIT_MASK1 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK2 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK3 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT_MASK3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK2 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK3 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BIT_STEP_DELTA_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_STEP_RANGE_EDGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_INCREASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_1D_EYE_NOISE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BAD_BIT_MASK3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK2 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK3 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT_MASK3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK2 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK3 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BIT_STEP_DELTA_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_STEP_RANGE_EDGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_INCREASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_1D_EYE_NOISE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BAD_BIT_MASK3 ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MAX_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_RANGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK2 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_TWO_RANGE_BEST_CASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK2 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BIT_STEP_DELTA_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_STEP_RANGE_EDGE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_INCREASE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK2 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_1D_EYE_NOISE_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK2 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BAD_BIT_MASK2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MAX_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_RANGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK3 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_TWO_RANGE_BEST_CASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK3 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BIT_STEP_DELTA_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_STEP_RANGE_EDGE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_INCREASE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK3 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_1D_EYE_NOISE_MASK3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BAD_BIT_MASK3 ); REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CTR_NUM_WRRDREQ_CNT ); @@ -18038,6 +18725,8 @@ REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS , 61 , SH_UN SH_FLD_DDR4_IPW_LOOP_DIS ); REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DDR4_VLEVEL_BANK_GROUP ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_VPROTH_PSEL_MODE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VPROTH_PSEL_MODE ); REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_WRITE_LATENCY_OFFSET ); @@ -19122,6 +19811,10 @@ REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_WL , 48 , SH_UN SH_FLD_WL ); REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CTR ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CTR_VREF_COUNTER_RESET_VAL ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL_LEN , 10 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_CTR_VREF_COUNTER_RESET_VAL_LEN ); REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DELAYG ); @@ -21669,8 +22362,8 @@ REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN , 2 , SH_UN SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN ); REG64_FLD( MCA_MBAREF0Q_CFG_PER_BANK_REFRESH , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_PER_BANK_REFRESH ); -REG64_FLD( MCA_MBAREF0Q_RESERVED_4 , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_4 ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_DEBUG_SELECT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_DEBUG_SELECT ); REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD ); REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -21919,10 +22612,12 @@ REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_SPEC_ATTN , 59 , SH_UN SH_FLD_CFG_ENABLE_SPEC_ATTN ); REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_HOST_ATTN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_ENABLE_HOST_ATTN ); -REG64_FLD( MCA_MBA_CAL0Q_RESERVED_61_63 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_61_63 ); -REG64_FLD( MCA_MBA_CAL0Q_RESERVED_61_63_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_61_63_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_DISABLE_RESET_RECOVER , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DISABLE_RESET_RECOVER ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_62_63 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63 ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_62_63_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63_LEN ); REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE ); @@ -22276,28 +22971,30 @@ REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL_SM_1HOT , 13 , SH_UN SH_FLD_CAL_SM_1HOT ); REG64_FLD( MCA_MBA_ERR_REPORTQ_RANK_SM_1HOT , 14 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RANK_SM_1HOT ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_PC_CAL_REFFSM_1HOT , 15 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_PC_CAL_REFFSM_1HOT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_15 , 15 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_15 ); REG64_FLD( MCA_MBA_ERR_REPORTQ_PC_CAL_PCFSM_1HOT , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PC_CAL_PCFSM_1HOT ); REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_CAL_RECVFSM_1HOT , 17 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_FARB_CAL_RECVFSM_1HOT ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_SIR_CERR , 18 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_SIR_CERR ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL0_INVALID_ACCESS , 19 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_CAL0_INVALID_ACCESS ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL1_INVALID_ACCESS , 20 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_CAL1_INVALID_ACCESS ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL2_INVALID_ACCESS , 21 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_CAL2_INVALID_ACCESS ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL3_INVALID_ACCESS , 22 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_CAL3_INVALID_ACCESS ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_DDR_INVALID_ACCESS , 23 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_DDR_INVALID_ACCESS ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_CERR_24 , 24 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_CERR_24 ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_CERR_25 , 25 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_CERR_25 ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_18_23 , 18 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_18_23 ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_18_23_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_18_23_LEN ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RCMD_ASYNC_IF , 24 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RCMD_ASYNC_IF ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_PF_PROMOTE_ASYNC_IF , 25 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PF_PROMOTE_ASYNC_IF ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_26 , 26 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_26 ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT , 27 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FARB_CMD_PE_HOLD_OUT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT , 28 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DSM_CMD_PE_HOLD_OUT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_29_30 , 29 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_29_30 ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_29_30_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_29_30_LEN ); REG64_FLD( MCA_MBA_FARB0Q_CFG_MISR_BLOCK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_MISR_BLOCK ); @@ -22347,8 +23044,8 @@ REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALWAYS_ON , 55 , SH_UN SH_FLD_CFG_OE_ALWAYS_ON ); REG64_FLD( MCA_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_FARB_CLOSE_ALL_PAGES ); -REG64_FLD( MCA_MBA_FARB0Q_RESERVED_57 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_57 ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PORT_FAIL_DISABLE ); REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALL_CKE_POWERED_DOWN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN ); REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -22606,14 +23303,11 @@ REG64_FLD( MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN , 5 , SH_UN REG64_FLD( MCA_MBA_FARB6Q_RESERVED_31 , 31 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RESERVED_31 ); -REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP , 0 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_EMER_THROTTLE_IP ); -REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE , 1 , SH_UNT_MCA , SH_ACS_SCOM , + +REG64_FLD( MCA_MBA_FARB8Q_SAFE_REFRESH_MODE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_SAFE_REFRESH_MODE ); -REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP_CLR , 2 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_EMER_THROTTLE_IP_CLR ); -REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE_CLR , 3 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_SAFE_REFRESH_MODE_CLR ); REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_FIR_CCS_ERR_HOLD_OUT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT ); @@ -24052,8 +24746,8 @@ REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED , 4 , SH_UN SH_FLD_CFG_DATA_ROT_SEED ); REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_DATA_ROT_SEED_LEN ); -REG64_FLD( MCBIST_MCBDRCRQ_CFG_INVERT_DATA , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_CFG_INVERT_DATA ); +REG64_FLD( MCBIST_MCBDRCRQ_RESERVED_20 , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_20 ); REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_DATA_SEED_MODE ); REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -25255,6 +25949,20 @@ REG64_FLD( MCBIST_MCB_CNTLSTATQ_DONE , 1 , SH_UN REG64_FLD( MCBIST_MCB_CNTLSTATQ_FAIL , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_FAIL ); +REG64_FLD( MCS_MCDBG0_DEBUG_BUS_0_63 , 0 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DEBUG_BUS_0_63 ); +REG64_FLD( MCS_MCDBG0_DEBUG_BUS_0_63_LEN , 64 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DEBUG_BUS_0_63_LEN ); + +REG64_FLD( MCS_MCDBG1_DEBUG_BUS_64_87 , 0 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DEBUG_BUS_64_87 ); +REG64_FLD( MCS_MCDBG1_DEBUG_BUS_64_87_LEN , 24 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DEBUG_BUS_64_87_LEN ); +REG64_FLD( MCS_MCDBG1_WRQ0_EMPTY , 24 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_WRQ0_EMPTY ); +REG64_FLD( MCS_MCDBG1_WRQ1_EMPTY , 25 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_WRQ1_EMPTY ); + REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE0_SEL , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_BYTE0_SEL ); REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE0_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , @@ -25283,6 +25991,8 @@ REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHC , 24 , SH_UN SH_FLD_LAT_THRESHC ); REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHC_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_LAT_THRESHC_LEN ); +REG64_FLD( MCS_PORT02_MCEBUSCL_SCOM20A_SEL , 32 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_SCOM20A_SEL ); REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE0_SEL , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_BYTE0_SEL ); @@ -25312,6 +26022,8 @@ REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHC , 24 , SH_UN SH_FLD_LAT_THRESHC ); REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHC_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_LAT_THRESHC_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSCL_SCOM20A_SEL , 32 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_SCOM20A_SEL ); REG64_FLD( MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , SH_FLD_EVENT_BUS_SELECTS ); @@ -25385,6 +26097,21 @@ REG64_FLD( MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON , 40 , SH_UN REG64_FLD( MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_VECTOR_GROUP_EPSILON_LEN ); +REG64_FLD( MCS_MCERPT0_DATA , 0 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCS_MCERPT0_DATA_LEN , 63 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( MCS_MCERPT1_DATA , 0 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCS_MCERPT1_DATA_LEN , 63 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( MCS_MCERPT2_DATA , 0 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCS_MCERPT2_DATA_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + REG64_FLD( MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0 , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_WDF_ERR_INJECT0 ); REG64_FLD( MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , @@ -25607,21 +26334,15 @@ REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT , 0 , SH_UN SH_FLD_RETRY_LPC_LFSR_SELECT ); REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RETRY_LPC_LFSR_SELECT_LEN ); -REG64_FLD( MCS_MCLFSR_ENABLE_READ_LFSR_DATA , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_READ_LFSR_DATA ); -REG64_FLD( MCS_MCLFSR_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR ); -REG64_FLD( MCS_MCLFSR_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR ); -REG64_FLD( MCS_MCLFSR_RESERVED515 , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED515 ); -REG64_FLD( MCS_MCLFSR_RESERVED515_LEN , 11 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED515_LEN ); - -REG64_FLD( MCS_MCMODE0_DIRECT_ATTACH_MODE , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_DIRECT_ATTACH_MODE ); -REG64_FLD( MCS_MCMODE0_CENTAUR_MODE , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCLFSR_RESERVED2_15 , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED2_15 ); +REG64_FLD( MCS_MCLFSR_RESERVED2_15_LEN , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED2_15_LEN ); + +REG64_FLD( MCS_MCMODE0_CENTAUR_MODE , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_CENTAUR_MODE ); +REG64_FLD( MCS_MCMODE0_RESERVED1 , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1 ); REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_CP_ME , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_CENTAURP_ENABLE_CP_ME ); REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_NEW_AMO , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -25652,10 +26373,10 @@ REG64_FLD( MCS_MCMODE0_SYNC_FENCE , 15 , SH_UN SH_FLD_SYNC_FENCE ); REG64_FLD( MCS_MCMODE0_ECRESP_HASH_MODE , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_ECRESP_HASH_MODE ); -REG64_FLD( MCS_MCMODE0_RESERVED17 , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED17 ); -REG64_FLD( MCS_MCMODE0_RESERVED18 , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED18 ); +REG64_FLD( MCS_MCMODE0_FORCE_ANY_CL_ACTIVE , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_FORCE_ANY_CL_ACTIVE ); +REG64_FLD( MCS_MCMODE0_FORCE_ANY_BAR_ACTIVE , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_FORCE_ANY_BAR_ACTIVE ); REG64_FLD( MCS_MCMODE0_MCS_RESET_KEEPER , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_MCS_RESET_KEEPER ); REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_SYNC , 20 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -25666,12 +26387,12 @@ REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_CHECKSTOP_COMMAND , 22 , SH_UN SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND ); REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_TRACESTOP_COMMAND , 23 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND ); -REG64_FLD( MCS_MCMODE0_RESERVED24 , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED24 ); +REG64_FLD( MCS_MCMODE0_ENABLE_ENABLE_CRESP_PE , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_ENABLE_CRESP_PE ); REG64_FLD( MCS_MCMODE0_RESERVED25 , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RESERVED25 ); -REG64_FLD( MCS_MCMODE0_DISABLE_CL_AO_QUEUES , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_DISABLE_CL_AO_QUEUES ); +REG64_FLD( MCS_MCMODE0_RESERVED26 , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED26 ); REG64_FLD( MCS_MCMODE0_RESERVED27 , 27 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RESERVED27 ); REG64_FLD( MCS_MCMODE0_RESERVED28 , 28 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -25756,20 +26477,22 @@ REG64_FLD( MCS_MCMODE2_DISABLE_MDI0 , 1 , SH_UN SH_FLD_DISABLE_MDI0 ); REG64_FLD( MCS_MCMODE2_DISABLE_MDI0_LEN , 13 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_MDI0_LEN ); -REG64_FLD( MCS_MCMODE2_DISABLE_CENTAUR_BAD_CRESP , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_DISABLE_CENTAUR_BAD_CRESP ); -REG64_FLD( MCS_MCMODE2_ENABLE_CRC_BYPASS_ALWAYS , 15 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_CRC_BYPASS_ALWAYS ); +REG64_FLD( MCS_MCMODE2_RESERVED14 , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED14 ); +REG64_FLD( MCS_MCMODE2_RESERVED15 , 15 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED15 ); REG64_FLD( MCS_MCMODE2_DISABLE_SHARD_PRESP_ABORT , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_SHARD_PRESP_ABORT ); REG64_FLD( MCS_MCMODE2_DISABLE_RETRY_LOST_CLAIM , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_RETRY_LOST_CLAIM ); REG64_FLD( MCS_MCMODE2_DOUBLE_EPSILON_LENGTH , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DOUBLE_EPSILON_LENGTH ); -REG64_FLD( MCS_MCMODE2_RESERVED19_23 , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED19_23 ); -REG64_FLD( MCS_MCMODE2_RESERVED19_23_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED19_23_LEN ); +REG64_FLD( MCS_MCMODE2_RESERVED19_22 , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED19_22 ); +REG64_FLD( MCS_MCMODE2_RESERVED19_22_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED19_22_LEN ); +REG64_FLD( MCS_MCMODE2_ENABLE_OP_HIT_ERROR , 23 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_OP_HIT_ERROR ); REG64_FLD( MCS_MCMODE2_COLLISION_MODES , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_COLLISION_MODES ); REG64_FLD( MCS_MCMODE2_COLLISION_MODES_LEN , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -26189,18 +26912,10 @@ REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN , 4 , SH_UN SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN ); REG64_FLD( MCS_MCPERF1_SPEC_READ_FILTER_NO_HASH_MODE , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE ); -REG64_FLD( MCS_MCPERF1_READ_SPECULATION_DISABLE_THRESHOLD , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD ); -REG64_FLD( MCS_MCPERF1_READ_SPECULATION_DISABLE_THRESHOLD_LEN , 6 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD_LEN ); -REG64_FLD( MCS_MCPERF1_RESERVED25 , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED25 ); -REG64_FLD( MCS_MCPERF1_READ_RAMP_PERF_TRESHOLD , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_READ_RAMP_PERF_TRESHOLD ); -REG64_FLD( MCS_MCPERF1_READ_RAMP_PERF_TRESHOLD_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_READ_RAMP_PERF_TRESHOLD_LEN ); -REG64_FLD( MCS_MCPERF1_ENABLE_DISABLE_PREFETCH_FOR_MIRROR_READS , 31 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_DISABLE_PREFETCH_FOR_MIRROR_READS ); +REG64_FLD( MCS_MCPERF1_RESERVED19_31 , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED19_31 ); +REG64_FLD( MCS_MCPERF1_RESERVED19_31_LEN , 13 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED19_31_LEN ); REG64_FLD( MCS_MCPERF1_PF_DROP_CNT_THRESH , 32 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_PF_DROP_CNT_THRESH ); REG64_FLD( MCS_MCPERF1_PF_DROP_CNT_THRESH_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -26298,10 +27013,12 @@ REG64_FLD( MCS_PORT02_MCPERF2_RMW_BUF_THRESH , 55 , SH_UN SH_FLD_RMW_BUF_THRESH ); REG64_FLD( MCS_PORT02_MCPERF2_RMW_BUF_THRESH_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_RMW_BUF_THRESH_LEN ); -REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_60_62 , 60 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_60_62 ); -REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_60_62_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_60_62_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_ALT_ECR_NO_ERR , 60 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_ALT_ECR_NO_ERR ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_ALT_ECR_ERR , 61 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_ALT_ECR_ERR ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_ALT_CR , 62 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_ALT_CR ); REG64_FLD( MCS_PORT02_MCPERF2_LOAD_RSVD_VALUES , 63 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_LOAD_RSVD_VALUES ); @@ -26375,10 +27092,12 @@ REG64_FLD( MCS_PORT13_MCPERF2_RMW_BUF_THRESH , 55 , SH_UN SH_FLD_RMW_BUF_THRESH ); REG64_FLD( MCS_PORT13_MCPERF2_RMW_BUF_THRESH_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_RMW_BUF_THRESH_LEN ); -REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_60_62 , 60 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_60_62 ); -REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_60_62_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_60_62_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_ALT_ECR_NO_ERR , 60 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_ALT_ECR_NO_ERR ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_ALT_ECR_ERR , 61 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_ALT_ECR_ERR ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_ALT_CR , 62 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_ALT_CR ); REG64_FLD( MCS_PORT13_MCPERF2_LOAD_RSVD_VALUES , 63 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_LOAD_RSVD_VALUES ); @@ -26485,6 +27204,47 @@ REG64_FLD( MCS_MCSYNC_SYNC_RESERVED , 25 , SH_UN REG64_FLD( MCS_MCSYNC_SYNC_RESERVED_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_SYNC_RESERVED_LEN ); +REG64_FLD( MCS_MCTEST_RESERVED0_3 , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED0_3 ); +REG64_FLD( MCS_MCTEST_RESERVED0_3_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED0_3_LEN ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_ALL_SPEC , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_ALL_SPEC ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_ALL_SPEC_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_ALL_SPEC_LEN ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_READ_BYP , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_READ_BYP ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_READ_BYP_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_READ_BYP_LEN ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_PREFETCH , 12 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_PREFETCH ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_PREFETCH_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_PREFETCH_LEN ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_FASTPATH , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_FASTPATH ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_FASTPATH_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_DIS_FASTPATH_LEN ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_SFSTAT , 20 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_FORCE_SFSTAT ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_SFSTAT_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_FORCE_SFSTAT_LEN ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_MDI , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_FORCE_MDI ); +REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_MDI_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WAT_ACTION_FORCE_MDI_LEN ); +REG64_FLD( MCS_MCTEST_RESERVED28_31 , 28 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED28_31 ); +REG64_FLD( MCS_MCTEST_RESERVED28_31_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED28_31_LEN ); +REG64_FLD( MCS_MCTEST_RCTRL_WAT_ACTION_SEL , 32 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RCTRL_WAT_ACTION_SEL ); +REG64_FLD( MCS_MCTEST_RCTRL_WAT_ACTION_SEL_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RCTRL_WAT_ACTION_SEL_LEN ); +REG64_FLD( MCS_MCTEST_RESERVED36_47 , 36 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED36_47 ); +REG64_FLD( MCS_MCTEST_RESERVED36_47_LEN , 12 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED36_47_LEN ); + REG64_FLD( MCS_MCTO_SELECT_PB_HANG_PULSE , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_SELECT_PB_HANG_PULSE ); REG64_FLD( MCS_MCTO_SELECT_LOCAL_HANG_PULSE , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -26639,6 +27399,11 @@ REG64_FLD( MCS_MCWATCNTL_RESERVED_39_63 , 39 , SH_UN REG64_FLD( MCS_MCWATCNTL_RESERVED_39_63_LEN , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RESERVED_39_63_LEN ); +REG64_FLD( MCS_MCWATDATA_MCWATDATA0 , 0 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_MCWATDATA0 ); +REG64_FLD( MCS_MCWATDATA_MCWATDATA0_LEN , 40 , SH_UNT_MCS , SH_ACS_SCOM_RO , + SH_FLD_MCWATDATA0_LEN ); + REG64_FLD( MCA_MSR_CHIPMARK , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CHIPMARK ); REG64_FLD( MCA_MSR_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , @@ -26648,6 +27413,79 @@ REG64_FLD( MCA_MSR_RANK , 16 , SH_UN REG64_FLD( MCA_MSR_RANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RANK_LEN ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0 ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0_LEN ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1 ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1_LEN ); + +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0 ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0_LEN ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1 ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1_LEN ); + +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_CKSTP , 48 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_FSM_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_CKSTP , 49 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_PARITY_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_CALIBRATION_ERROR , 50 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_CALIBRATION_ERROR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_ERR , 51 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_FSM_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_ERR , 52 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_PARITY_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR01_PARITY_ERR , 53 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR01_PARITY_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_CKSTP , 56 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_FSM_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_CKSTP , 57 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_PARITY_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_CALIBRATION_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_CALIBRATION_ERROR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_ERR , 59 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_FSM_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_ERR , 60 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_PARITY_ERR ); + +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_FSM_CKSTP , 48 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_FSM_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_PARITY_CKSTP , 49 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_PARITY_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_CALIBRATION_ERROR , 50 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_CALIBRATION_ERROR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_FSM_ERR , 51 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_FSM_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_PARITY_ERR , 52 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_PARITY_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR01_PARITY_ERR , 53 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR01_PARITY_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_FSM_CKSTP , 56 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_FSM_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_PARITY_CKSTP , 57 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_PARITY_CKSTP ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_CALIBRATION_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_CALIBRATION_ERROR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_FSM_ERR , 59 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_FSM_ERR ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_PARITY_ERR , 60 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_PARITY_ERR ); + +REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR0 ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR0_LEN ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR1 ); +REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR1_LEN ); + REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_MCA , SH_ACS_SCOM , @@ -26856,8 +27694,8 @@ REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_UE_RETRY , 3 , SH_UN SH_FLD_MBSECCQ_DISABLE_UE_RETRY ); REG64_FLD( MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE ); -REG64_FLD( MCA_RECR_MBSECCQ_INT_RESET_KEEPER , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_INT_RESET_KEEPER ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_5 , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_5 ); REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_READ_POINTER_DELAY ); REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -26911,9 +27749,11 @@ REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39 , 33 , SH_UN REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_RESERVED_33_39_LEN ); -REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_DISABLED ); +REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -27045,6 +27885,122 @@ REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_ REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL ); +REG64_FLD( MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL_LEN , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL_LEN ); + +REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_MSKA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA ); +REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_MSKA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA_LEN ); +REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_CNTL , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL ); +REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_CNTL_LEN , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL_LEN ); + +REG64_FLD( MCBIST_WATCFG0CQ_CFG_WAT_MSKB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB ); +REG64_FLD( MCBIST_WATCFG0CQ_CFG_WAT_MSKB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB_LEN ); + +REG64_FLD( MCBIST_WATCFG0DQ_CFG_WAT_PATA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA ); +REG64_FLD( MCBIST_WATCFG0DQ_CFG_WAT_PATA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA_LEN ); + +REG64_FLD( MCBIST_WATCFG0EQ_CFG_WAT_PATB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB ); +REG64_FLD( MCBIST_WATCFG0EQ_CFG_WAT_PATB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB_LEN ); + +REG64_FLD( MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL ); +REG64_FLD( MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL_LEN , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL_LEN ); + +REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_MSKA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA ); +REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_MSKA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA_LEN ); +REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_CNTL , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL ); +REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_CNTL_LEN , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL_LEN ); + +REG64_FLD( MCBIST_WATCFG1CQ_CFG_WAT_MSKB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB ); +REG64_FLD( MCBIST_WATCFG1CQ_CFG_WAT_MSKB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB_LEN ); + +REG64_FLD( MCBIST_WATCFG1DQ_CFG_WAT_PATA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA ); +REG64_FLD( MCBIST_WATCFG1DQ_CFG_WAT_PATA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA_LEN ); + +REG64_FLD( MCBIST_WATCFG1EQ_CFG_WAT_PATB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB ); +REG64_FLD( MCBIST_WATCFG1EQ_CFG_WAT_PATB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB_LEN ); + +REG64_FLD( MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL ); +REG64_FLD( MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL_LEN , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL_LEN ); + +REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_MSKA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA ); +REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_MSKA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA_LEN ); +REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_CNTL , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL ); +REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_CNTL_LEN , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL_LEN ); + +REG64_FLD( MCBIST_WATCFG2CQ_CFG_WAT_MSKB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB ); +REG64_FLD( MCBIST_WATCFG2CQ_CFG_WAT_MSKB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB_LEN ); + +REG64_FLD( MCBIST_WATCFG2DQ_CFG_WAT_PATA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA ); +REG64_FLD( MCBIST_WATCFG2DQ_CFG_WAT_PATA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA_LEN ); + +REG64_FLD( MCBIST_WATCFG2EQ_CFG_WAT_PATB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB ); +REG64_FLD( MCBIST_WATCFG2EQ_CFG_WAT_PATB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB_LEN ); + +REG64_FLD( MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL ); +REG64_FLD( MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL_LEN , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EVENT_SEL_LEN ); + +REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_MSKA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA ); +REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_MSKA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKA_LEN ); +REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_CNTL , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL ); +REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_CNTL_LEN , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CNTL_LEN ); + +REG64_FLD( MCBIST_WATCFG3CQ_CFG_WAT_MSKB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB ); +REG64_FLD( MCBIST_WATCFG3CQ_CFG_WAT_MSKB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_MSKB_LEN ); + +REG64_FLD( MCBIST_WATCFG3DQ_CFG_WAT_PATA , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA ); +REG64_FLD( MCBIST_WATCFG3DQ_CFG_WAT_PATA_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATA_LEN ); + +REG64_FLD( MCBIST_WATCFG3EQ_CFG_WAT_PATB , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB ); +REG64_FLD( MCBIST_WATCFG3EQ_CFG_WAT_PATB_LEN , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PATB_LEN ); + REG64_FLD( MCA_WBMGR_TAG_INFO_BUFFER_OVERRUN , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_BUFFER_OVERRUN ); REG64_FLD( MCA_WBMGR_TAG_INFO_OVERRUN , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , |
