diff options
| author | Ben Gass <bgass@us.ibm.com> | 2015-08-18 15:03:28 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-02-22 15:14:06 -0600 |
| commit | e81ba9b7a10338bf9e1c5be57866dad4c0159539 (patch) | |
| tree | fd37c910103a806d676199e7c23216bad51b0454 /src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H | |
| parent | e0bec1ab9bf8162cad8194326cd1c26a06938748 (diff) | |
| download | talos-hostboot-e81ba9b7a10338bf9e1c5be57866dad4c0159539.tar.gz talos-hostboot-e81ba9b7a10338bf9e1c5be57866dad4c0159539.zip | |
Generated from n10_e9024_tp023_spider_u223_01
Updates to scom address translation code were also included.
Fixes from previous builds should have been maintained.
Change-Id: I2ecd6578d12ee9877b6af5e513a42a9e72cf9d0a
Original-Change-Id: I8063105bfad25c4ba19f8117e73ff99cdc4060a4
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19906
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24595
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H | 24977 |
1 files changed, 24977 insertions, 0 deletions
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H new file mode 100644 index 000000000..9452f4a05 --- /dev/null +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H @@ -0,0 +1,24977 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/common/include/p9_mc_scom_addresses_fld.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_mc_scom_addresses_fld.H +/// @brief Defines constants for scom addresses +/// +// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: SOA +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE +#ifndef __P9_MC_SCOM_ADDRESSES_FLD_H +#define __P9_MC_SCOM_ADDRESSES_FLD_H + + +#include <p9_scom_template_consts.H> +#include <p9_mc_scom_addresses_fld_fixes.H> + +REG64_FLD( MCS_PORT02_AACR_BUFFER , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW , + SH_FLD_BUFFER ); +REG64_FLD( MCS_PORT02_AACR_ADDRESS , 1 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCS_PORT02_AACR_ADDRESS_LEN , 9 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCS_PORT02_AACR_AUTOINC , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW , + SH_FLD_AUTOINC ); + +REG64_FLD( MCA_WREITE_AACR_BUFFER , 0 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_BUFFER ); +REG64_FLD( MCA_WREITE_AACR_ADDRESS , 1 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_WREITE_AACR_ADDRESS_LEN , 9 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_WREITE_AACR_AUTOINC , 10 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_AUTOINC ); +REG64_FLD( MCA_WREITE_AACR_ECCGEN , 11 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_ECCGEN ); + +REG64_FLD( MCS_PORT02_AADR_DATA , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCS_PORT02_AADR_DATA_LEN , 64 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( MCA_AADR_DATA , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DATA ); +REG64_FLD( MCA_AADR_DATA_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DATA_LEN ); + +REG64_FLD( MCS_PORT02_AAER_TAG_ECC , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO , + SH_FLD_TAG_ECC ); +REG64_FLD( MCS_PORT02_AAER_TAG_ECC_LEN , 9 , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO , + SH_FLD_TAG_ECC_LEN ); + +REG64_FLD( MCA_AAER_TAG_ECC , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TAG_ECC ); +REG64_FLD( MCA_AAER_TAG_ECC_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TAG_ECC_LEN ); + +REG64_FLD( MCA_ACTION0_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FIR ); +REG64_FLD( MCA_ACTION0_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FIR_LEN ); + +REG64_FLD( MCA_ACTION1_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FIR ); +REG64_FLD( MCA_ACTION1_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FIR_LEN ); + +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_ARRAY_CE_ERR_INJ ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_ARRAY_UE_ERR_INJ ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CS_CHIP_ID_2N_MODE , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CS_CHIP_ID_2N_MODE ); +REG64_FLD( MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_2N_MODE ); +REG64_FLD( MCBIST_CCSARRERRINJQ_RESERVED_6_14 , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_14 ); +REG64_FLD( MCBIST_CCSARRERRINJQ_RESERVED_6_14_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_14_LEN ); +REG64_FLD( MCBIST_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_RESPONSE_DELAY_ENABLE ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_LOOP_COUNTER_COMPARE0 ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_LOOP_COUNTER_COMPARE1 ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_LOOP_COUNTER_COMPARE2 ); +REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN ); + +REG64_FLD( MCBIST_CCS_CNTLQ_START , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_START ); +REG64_FLD( MCBIST_CCS_CNTLQ_STOP , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_STOP ); + +REG64_FLD( MCBIST_CCS_FIXED_DATA0Q_DATA_0_63 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DATA_0_63 ); +REG64_FLD( MCBIST_CCS_FIXED_DATA0Q_DATA_0_63_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DATA_0_63_LEN ); + +REG64_FLD( MCBIST_CCS_FIXED_DATA1Q_DATA_64_79 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DATA_64_79 ); +REG64_FLD( MCBIST_CCS_FIXED_DATA1Q_DATA_64_79_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DATA_64_79_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_28_31 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_28_31_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_17 , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_1 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_RESETN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_RESETN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_0 , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ACTN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ACTN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_16 , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_15 , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_14 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CKE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CKE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CKE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_28 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_28_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_0_1_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CSN_2_3_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CID_2 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CID_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_39_47 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_39_47_LEN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39_47_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ODT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ODT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_ODT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_52_55 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_52_55_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52_55_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_PARITY , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_2 , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_BANK_2 ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE ); +REG64_FLD( MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LOOP_BREAK_MODE_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_00_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_01_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_01_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_02_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_02_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_03_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_03_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_04_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_04_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_05_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_05_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_06_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_06_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_07_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_07_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_08_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_08_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_09_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_09_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_10_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_10_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_11_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_11_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_12_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_12_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_13_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_13_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_14_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_14_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_15_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_15_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_16_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_16_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_17_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_17_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_18_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_18_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_19_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_19_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_20_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_20_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_21_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_21_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_22_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_22_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_23_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_23_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_24_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_24_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_25_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_25_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_26_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_26_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_27_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_27_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_28_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_28_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_29_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_29_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_30_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_30_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_INST_ARR1_31_IDLES , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_IDLES_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLES_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REPEAT_CMD_CNT_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_OR_WRITE_DATA_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_READ_COMPARE_REQUIRED ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_RANK_LEN ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_DDR_CALIBRATION_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CALIBRATION_ENABLE ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_END , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_END ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_GOTO_CMD , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD ); +REG64_FLD( MCBIST_CCS_INST_ARR1_31_GOTO_CMD_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_GOTO_CMD_LEN ); + +REG64_FLD( MCBIST_CCS_MODEQ_STOP_ON_ERR , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_STOP_ON_ERR ); +REG64_FLD( MCBIST_CCS_MODEQ_UE_DISABLE , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_UE_DISABLE ); +REG64_FLD( MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DATA_COMPARE_BURST_SEL ); +REG64_FLD( MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DATA_COMPARE_BURST_SEL_LEN ); +REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_4_7 , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_4_7 ); +REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_4_7_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_4_7_LEN ); +REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TIMEOUT_CNT ); +REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN ); +REG64_FLD( MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARITY_AFTER_CMD ); +REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_25 , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_25 ); +REG64_FLD( MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE , 26 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_COPY_CKE_TO_SPARE_CKE ); +REG64_FLD( MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK , 27 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_ECC_ARRAY_CHK ); +REG64_FLD( MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_ECC_ARRAY_CORRECTION ); +REG64_FLD( MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DGEN_FIXED_MODE ); +REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT ); +REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_ADDRESS_0_13 ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17 , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_ADDRESS_17 ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1 , 47 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_BANK_GROUP_1 ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_BANK_0_1 ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_BANK_0_1_LEN ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0 , 50 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_BANK_GROUP_0 ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ACTN , 51 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_ACTN ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_ADDRESS_16 ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15 , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_ADDRESS_15 ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14 , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_ADDRESS_14 ); +REG64_FLD( MCBIST_CCS_MODEQ_NTTM_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_NTTM_MODE ); +REG64_FLD( MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_NTTM_RW_DATA_DLY ); +REG64_FLD( MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_NTTM_RW_DATA_DLY_LEN ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2 , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_BANK_2 ); +REG64_FLD( MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DDR_PARITY_ENABLE ); +REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_PARITY , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IDLE_PAT_PARITY ); +REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_63 , 63 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_63 ); + +REG64_FLD( MCBIST_CCS_STATQ_IP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IP ); +REG64_FLD( MCBIST_CCS_STATQ_DONE , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DONE ); +REG64_FLD( MCBIST_CCS_STATQ_FAIL , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FAIL ); +REG64_FLD( MCBIST_CCS_STATQ_FAIL_TYPE , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FAIL_TYPE ); +REG64_FLD( MCBIST_CCS_STATQ_FAIL_TYPE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FAIL_TYPE_LEN ); +REG64_FLD( MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_SUBTEST_IP ); + +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_0_11 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_0_11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_12_15 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_12_15 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_12_15_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_12_15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_0_11 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_0_11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_12_15 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_12_15 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_12_15_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_12_15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_0_11 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_0_11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_12_15 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_12_15 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_12_15_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_12_15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_0_11 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_0_11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_12_15 ); +REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_12_15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY1 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY1 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY1 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY1 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY2 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY3 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY2 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY3 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY2 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY3 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY2 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY3 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY4 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY5 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY4 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY5 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY4 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY5 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY4 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY5 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY6 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY7 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY6 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY7 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY6 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY7 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY6 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY7 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY8 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY9 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY9_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY8 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY9 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY9_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY8 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY9 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY9_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY8 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY9 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY9_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY10 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY11 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY11_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY10 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY11 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY11_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY10 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY11 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY11_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY10 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY11 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY11_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY12 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY13 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY13_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY12 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY13 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY13_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY12 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY13 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY13_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY12 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY13 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY13_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY14 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY15 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY14 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY15 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY14 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY15 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY14 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY15 ); +REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL , 48 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_01_TEST_LANE_PAIR_FAIL ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_DATA_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_DATA_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE , 57 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_4TO1_MODE , 59 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_4TO1_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_RESET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_GEN_EN , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_GEN_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CLEAR_ERROR , 62 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_01_TEST_CLEAR_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CHECK_EN , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_CHECK_EN ); + +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL , 48 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_01_TEST_LANE_PAIR_FAIL ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_DATA_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_DATA_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE , 57 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_4TO1_MODE , 59 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_4TO1_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_RESET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_GEN_EN , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_GEN_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CLEAR_ERROR , 62 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_01_TEST_CLEAR_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CHECK_EN , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TEST_CHECK_EN ); + +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL , 48 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_23_TEST_LANE_PAIR_FAIL ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_DATA_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_DATA_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE , 57 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_4TO1_MODE , 59 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_4TO1_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_RESET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_GEN_EN , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_GEN_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CLEAR_ERROR , 62 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_23_TEST_CLEAR_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CHECK_EN , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_CHECK_EN ); + +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL , 48 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_23_TEST_LANE_PAIR_FAIL ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_DATA_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_DATA_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE , 57 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_4TO1_MODE , 59 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_4TO1_MODE ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_RESET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_GEN_EN , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_GEN_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CLEAR_ERROR , 62 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_23_TEST_CLEAR_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CHECK_EN , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TEST_CHECK_EN ); + +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR1 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR2_ADR3 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR2_ADR3 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR4_ADR5 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR4_ADR5 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR6_ADR7 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR6_ADR7 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR8_ADR9 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR8_ADR9 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR10_ADR11 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR10_ADR11 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR12_ADR13 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR12_ADR13 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR14_ADR15 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR14_ADR15 ); + +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR0 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR2_ADR3 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR2_ADR3 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR4_ADR5 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR4_ADR5 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR6_ADR7 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR6_ADR7 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR8_ADR9 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR8_ADR9 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR10_ADR11 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR10_ADR11 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR12_ADR13 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR12_ADR13 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR14_ADR15 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DI_ADR14_ADR15 ); + +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR0_ADR1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR0_ADR1 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR3 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR3 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR4_ADR5 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR4_ADR5 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR6_ADR7 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR6_ADR7 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR8_ADR9 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR8_ADR9 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR10_ADR11 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR10_ADR11 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR12_ADR13 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR12_ADR13 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR14_ADR15 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR14_ADR15 ); + +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR0_ADR1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR0_ADR1 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR2 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR4_ADR5 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR4_ADR5 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR6_ADR7 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR6_ADR7 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR8_ADR9 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR8_ADR9 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR10_ADR11 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR10_ADR11 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR12_ADR13 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR12_ADR13 ); +REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR14_ADR15 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DI_ADR14_ADR15 ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_FRZSULV ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_FRZSULV ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_VREG ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_VREG_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_VREG ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_VREG_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_VREG ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_VREG_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_VREG ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_VREG_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_EN_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_DAC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_REGS_RXDLL_DAC_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_EN_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_DAC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_REGS_RXDLL_DAC_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_HS_DLLMUX_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_HS_DLLMUX_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ATEST_SEL_0 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_ATEST_SEL_0 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ATEST_SEL_0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_ATEST_SEL_0_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_INTERP_SIG_SLEW_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_INTERP_SIG_SLEW_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ANALOG_WRAPON , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_ANALOG_WRAPON ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_HS_DLLMUX_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_HS_DLLMUX_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ATEST_SEL_0 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_ATEST_SEL_0 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ATEST_SEL_0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_ATEST_SEL_0_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_INTERP_SIG_SLEW_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_INTERP_SIG_SLEW_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ANALOG_WRAPON , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_ANALOG_WRAPON ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL0_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL0_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL0_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL0 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL0_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL1 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL1_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL4 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL4_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL4_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL5_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL5_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL6 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL6_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL6_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL7 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL7_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL7_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL8_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL8_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL8_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL8 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL8 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL8_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL8_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL9 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL9_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL9_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL10_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL11_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL12_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL13_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL14_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15 ); +REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL15_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_TSYS ); +REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_TSYS_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_TSYS ); +REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_TSYS_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_VALUE ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_VALUE ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_VALUE ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_VALUE ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_FLUSH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_FLUSH ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_EN ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_INIT_IO , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_INIT_IO ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3 , 51 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_HS_PROBE_A_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_HS_PROBE_A_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3 , 55 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_HS_PROBE_B_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_HS_PROBE_B_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_ATESTSEL_0_2 ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_ATESTSEL_0_2_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_FLUSH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_FLUSH ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_EN ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_INIT_IO , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_INIT_IO ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3 , 51 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_HS_PROBE_A_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_HS_PROBE_A_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3 , 55 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_HS_PROBE_B_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_HS_PROBE_B_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_ATESTSEL_0_2 ); +REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_ATESTSEL_0_2_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_11_PD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__0_11_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_11_PD_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__0_11_PD_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__12_15_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__12_15_PD_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_11_PD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__0_11_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_11_PD_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__0_11_PD_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__12_15_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LANE__12_15_PD_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_11_PD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__0_11_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_11_PD_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__0_11_PD_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__12_15_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__12_15_PD_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_11_PD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__0_11_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_11_PD_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__0_11_PD_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__12_15_PD ); +REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LANE__12_15_PD_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_START , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_START ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE_EN , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_TARGET_PR_OFFSET , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_TARGET_PR_OFFSET ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_TARGET_PR_OFFSET_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_TARGET_PR_OFFSET_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_START , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_START ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE_EN , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_TARGET_PR_OFFSET ); +REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_TARGET_PR_OFFSET_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_ENABLE ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_PHASE_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_ENABLE ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_PHASE_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR0_ROT ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR0_ROT_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR0_BB_LOCK ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_ADR0_SLEW_DONE_STATUS ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_ADR0_SLEW_DONE_STATUS_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_RESERVED_60_63 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR0_RESERVED_60_63 ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_RESERVED_60_63_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_ADR0_RESERVED_60_63_LEN ); + +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR1_ROT ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR1_ROT_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_BB_LOCK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR1_BB_LOCK ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_ADR1_SLEW_DONE_STATUS ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_ADR1_SLEW_DONE_STATUS_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_RESERVED_60_63 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR1_RESERVED_60_63 ); +REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_RESERVED_60_63_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_ADR1_RESERVED_60_63_LEN ); + +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CNTL ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CNTL_LEN ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR0 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR1 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR1 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR2 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR3 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR4 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR4 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VPROTH_CTL ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VPROTH_CTL_LEN ); + +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DISABLE_PARITY_CHECKER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_PARITY_CHECKER ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_RESET_ERR_RPT , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESET_ERR_RPT ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_FORCE_ON_CLK_GATE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FORCE_ON_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_BUS_SEL ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_BUS_SEL_LEN ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_ADR_SLAVE_SEL , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR_SLAVE_SEL ); + +REG64_FLD( MCA_DDRPHY_APB_ERROR_MASK0_P0_INVALID_ADDRESS_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INVALID_ADDRESS_MASK ); +REG64_FLD( MCA_DDRPHY_APB_ERROR_MASK0_P0_WR_PAR_ERR_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WR_PAR_ERR_MASK ); + +REG64_FLD( MCA_DDRPHY_APB_ERROR_STATUS0_P0_INVALID_ADDRESS , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_INVALID_ADDRESS ); +REG64_FLD( MCA_DDRPHY_APB_ERROR_STATUS0_P0_WR_PAR_ERR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WR_PAR_ERR ); + +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_SET0 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET1 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_SET1 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_SET2 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET3 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_SET3 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET4 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_SET4 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET5 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_SET5 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP18 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_FSM_DP18 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP18_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_FSM_DP18_LEN ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP18 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_REG_DP18 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP18_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_REG_DP18_LEN ); + +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_ERR_STATUS0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PC_ERR_STATUS0 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_ERR_STATUS0_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PC_ERR_STATUS0_LEN ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PC_INIT_CAL_ERR ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PC_INIT_CAL_ERR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S0ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S0ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S0ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S0ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S0ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S0ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S1ACENSLICENDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S1ACENSLICENDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S1ACENSLICEPDRV_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S1ACENSLICEPDRV_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S1ACENSLICEPTERM_DC ); +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S1ACENSLICEPTERM_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_1_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_0_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_0_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB_1_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_0_2_DQSEL_RES_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_CAP ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_IND ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_IND_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_RES ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB_1_3_DQSEL_RES_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0_01_DIR_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DIR_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0_01_DIR_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DIR_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_1_01_DIR_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DIR_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_1_01_DIR_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DIR_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_2_23_DIR_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DIR_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_2_23_DIR_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DIR_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_3_23_DIR_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DIR_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_3_23_DIR_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DIR_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_4_4_DIR_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DIR_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_4_4_DIR_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DIR_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FLUSH , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FLUSH ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FORCE_DQS_LANES_ON , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FORCE_DQS_LANES_ON ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DD2_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_INIT_IO , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_IO ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ADVANCE_PING_PONG , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ADVANCE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_WL_ADVANCE_DISABLE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ADVANCE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DISABLE_PING_PONG , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DELAY_PING_PONG_HALF , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY_PING_PONG_HALF ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ATESTSEL_4 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATESTSEL_4 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ATESTSEL_4_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATESTSEL_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_FLUSH , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FLUSH ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_FORCE_DQS_LANES_ON , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FORCE_DQS_LANES_ON ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_DD2_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_INIT_IO , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_IO ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_ADVANCE_PING_PONG , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ADVANCE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_WL_ADVANCE_DISABLE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ADVANCE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_DISABLE_PING_PONG , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_DELAY_PING_PONG_HALF , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAY_PING_PONG_HALF ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_ATESTSEL_0_4 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATESTSEL_0_4 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_ATESTSEL_0_4_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATESTSEL_0_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_FLUSH , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FLUSH ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_FORCE_DQS_LANES_ON , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FORCE_DQS_LANES_ON ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_DD2_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DD2_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_INIT_IO , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_IO ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_ADVANCE_PING_PONG , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ADVANCE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_WL_ADVANCE_DISABLE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ADVANCE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_DISABLE_PING_PONG , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_DELAY_PING_PONG_HALF , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY_PING_PONG_HALF ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_ATESTSEL_0_4 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATESTSEL_0_4 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_ATESTSEL_0_4_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATESTSEL_0_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_FLUSH , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FLUSH ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_FORCE_DQS_LANES_ON , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FORCE_DQS_LANES_ON ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_DD2_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DD2_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_INIT_IO , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_IO ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_ADVANCE_PING_PONG , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ADVANCE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_WL_ADVANCE_DISABLE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ADVANCE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_DISABLE_PING_PONG , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_DELAY_PING_PONG_HALF , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAY_PING_PONG_HALF ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_ATESTSEL_0_4 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATESTSEL_0_4 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_ATESTSEL_0_4_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATESTSEL_0_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_FLUSH , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_FLUSH ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_FORCE_DQS_LANES_ON , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_FORCE_DQS_LANES_ON ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_DD2_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DD2_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_INIT_IO , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INIT_IO ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_ADVANCE_PING_PONG , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ADVANCE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_WL_ADVANCE_DISABLE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ADVANCE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_DISABLE_PING_PONG , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_PING_PONG ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_DELAY_PING_PONG_HALF , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAY_PING_PONG_HALF ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_ATESTSEL_0 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ATESTSEL_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_ATESTSEL_0_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ATESTSEL_0_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0_01_DISABLE_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0_01_DISABLE_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1_01_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1_01_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4_4_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4_4_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0_01_DISABLE_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0_01_DISABLE_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1_01_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1_01_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4_4_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4_4_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0_01_DISABLE_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0_01_DISABLE_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1_01_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1_01_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4_4_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4_4_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0_01_DISABLE_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0_01_DISABLE_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1_01_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1_01_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3_23_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3_23_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4_4_DISABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4_4_DISABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4_4_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4_4_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4_4_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4_4_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4_4_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4_4_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1_01_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1_01_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3_23_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3_23_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4_4_DISABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4_4_DISABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0_01_ENABLE_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0_01_ENABLE_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1_01_ENABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1_01_ENABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2_23_ENABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2_23_ENABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3_23_ENABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3_23_ENABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4_4_ENABLE_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ENABLE_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4_4_ENABLE_0_15_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ENABLE_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_ENABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_ENABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_16_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_DFT_FORCE_OUTPUTS , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DFT_FORCE_OUTPUTS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_DFT_PRBS7_GEN_EN , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DFT_PRBS7_GEN_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_WRAPSEL , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WRAPSEL ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_HW_VALUE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HW_VALUE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N3 ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_ENABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_ENABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE_16_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_DFT_FORCE_OUTPUTS , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DFT_FORCE_OUTPUTS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_DFT_PRBS7_GEN_EN , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DFT_PRBS7_GEN_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_WRAPSEL , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WRAPSEL ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_HW_VALUE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HW_VALUE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N0 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N2 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MRS_CMD_N3 ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_ENABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_ENABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_16_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_DFT_FORCE_OUTPUTS , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DFT_FORCE_OUTPUTS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_DFT_PRBS7_GEN_EN , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DFT_PRBS7_GEN_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_WRAPSEL , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WRAPSEL ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_HW_VALUE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HW_VALUE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N0 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N2 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N3 ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_ENABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_ENABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE_16_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_DFT_FORCE_OUTPUTS , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DFT_FORCE_OUTPUTS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_DFT_PRBS7_GEN_EN , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DFT_PRBS7_GEN_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_WRAPSEL , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WRAPSEL ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_HW_VALUE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HW_VALUE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N0 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N2 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MRS_CMD_N3 ); + +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_ENABLE_16_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ENABLE_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_ENABLE_16_23_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ENABLE_16_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_DFT_FORCE_OUTPUTS , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DFT_FORCE_OUTPUTS ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_DFT_PRBS7_GEN_EN , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DFT_PRBS7_GEN_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_WRAPSEL , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WRAPSEL ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_HW_VALUE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HW_VALUE ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N0 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MRS_CMD_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N1 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MRS_CMD_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N2 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MRS_CMD_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MRS_CMD_N3 ); + +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_A ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_B ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_B_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_A ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_B ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_PROBE_B_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_A ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_B ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_B_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_A ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_B ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_PROBE_B_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_PROBE_A ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_PROBE_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_PROBE_B ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_PROBE_B_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3 ); +REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DIGITAL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_BUMP ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TRIG_PERIOD ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CNTL_POL ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CNTL_SRC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RESERVED_56_63 ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RESERVED_56_63_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DIGITAL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_BUMP ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_TRIG_PERIOD ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CNTL_POL ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CNTL_SRC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RESERVED_56_63 ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_RESERVED_56_63_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DIGITAL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_BUMP ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TRIG_PERIOD ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CNTL_POL ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CNTL_SRC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RESERVED_56_63 ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RESERVED_56_63_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DIGITAL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_BUMP ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_TRIG_PERIOD ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CNTL_POL ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CNTL_SRC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RESERVED_56_63 ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_RESERVED_56_63_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DIGITAL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_BUMP ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_TRIG_PERIOD ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CNTL_POL ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CNTL_SRC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_RESERVED_56_63 ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_RESERVED_56_63_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CHECKER_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_RESET , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CHECKER_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC , 52 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_SYNC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_SYNC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_ERROR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CHECKER_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_RESET , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CHECKER_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC , 52 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_SYNC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_SYNC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_ERROR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CHECKER_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_RESET , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CHECKER_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC , 52 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_SYNC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_SYNC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_ERROR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CHECKER_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_RESET , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CHECKER_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC , 52 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_SYNC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_SYNC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_ERROR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CHECKER_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_RESET , 49 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CHECKER_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC , 52 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_SYNC ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_SYNC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_ERROR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INIT_RXDLL_CAL_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INIT_RXDLL_CAL_UPDATE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_CAL_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_FILTER_LENGTH_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_DRIVER_INVFB_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_FRZSULV ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_GOOD ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_TUNEATST , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TUNEATST ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL1_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL1_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL1_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL1_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TUNEATST_1 ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL0_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL0_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TUNEATST_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL1_0_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL1_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL1_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S0INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_S1INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_TUNEATST , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TUNEATST ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL0_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL0_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TUNEATST_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL1_0_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL1_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL1_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TUNEATST_1 ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL0_0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL0_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL0_0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL0_0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TUNEATST_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL1_0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL1_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL1_0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL1_0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S0INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_S1INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TUNEATST_1 ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL0_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL0_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_TUNEATST_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL1_0_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL1_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL1_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S0INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_S1INSDLYTAP ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_TUNEATST_1 ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_LOWER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_UPPER ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_COARSE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_DAC_COARSE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_COMPCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_COMPCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_CON_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_CON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DAC_PULLUP_DC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_DAC_PULLUP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_DRVCON_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_DRVCON_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_REF_SEL_DC ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RXREG_REF_SEL_DC_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_CLK_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0 , 50 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1 , 52 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1 , 54 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2 , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2 , 58 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3 , 60 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DQSCLK_SELECT3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3 , 62 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_RDCLK_SELECT3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N1_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_N3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RD_EYE_SIZE ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RD_EYE_SIZE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RD_EYE_SIZE ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_RD_EYE_SIZE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MAX_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RD_EYE_SIZE ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RD_EYE_SIZE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RD_EYE_SIZE ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_RD_EYE_SIZE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MAX_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_RD_EYE_SIZE ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_RD_EYE_SIZE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MAX_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MAX_DQS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT_N1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INTERP_SIG_SLEW ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INTERP_SIG_SLEW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_INTERP_SIG_SLEW , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INTERP_SIG_SLEW ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INTERP_SIG_SLEW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_INTERP_SIG_SLEW , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INTERP_SIG_SLEW ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INTERP_SIG_SLEW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_INTERP_SIG_SLEW , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INTERP_SIG_SLEW ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INTERP_SIG_SLEW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_INTERP_SIG_SLEW , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INTERP_SIG_SLEW ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INTERP_SIG_SLEW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_N_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_N_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_4_4_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_4_4_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_N_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_4_4_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_4_4_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_P_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_P_WR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD00 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD00_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD01 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD02 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD02_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD03 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD03_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD04 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD04_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD05 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD05_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD06 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD06_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD07 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD07_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD00 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD00_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD01 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD02 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD02_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD03 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD03_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD04 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD04_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD05 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD05_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD06 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD06_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD07 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD07_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD00 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD00_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD01 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD02 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD02_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD03 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD03_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD04 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD04_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD05 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD05_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD06 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD06_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD07 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD07_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD00 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD00_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD01 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD02 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD02_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD03 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD03_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD04 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD04_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD05 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD05_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD06 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD06_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD07 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD07_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD00 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD00_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD01 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD02 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD02_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD03 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD03_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD04 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD04_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD05 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD05_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD06 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD06_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD07 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD07_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD08 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD08_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD09 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD09_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD10 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD10_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD11 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD11_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD12 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD12_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD13 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD13_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD14 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD14_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD15 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD08 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD08_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD09 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD09_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD10 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD10_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD11 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD11_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD12 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD12_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD13 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD13_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD14 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD14_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD15 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD08 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD08_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD09 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD09_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD10 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD10_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD11 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD11_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD12 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD12_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD13 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD13_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD14 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD14_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD15 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD08 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD08_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD09 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD09_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD10 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD10_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD11 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD11_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD12 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD12_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD13 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD13_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD14 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD14_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD15 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD08 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD08_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD09 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD09_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD10 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD10_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD11 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD11_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD12 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD12_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD13 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD13_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD14 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD14_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD15 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD16 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD16_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD16_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD17 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD17 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD17_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD17_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD18 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD18_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD18_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD19 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD19 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD19_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD19_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD20 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD20 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD20_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD20_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD21 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD21 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD21_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD21_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD22 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD22 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD22_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD22_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD23 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD23 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD23_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD16 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD16_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD16_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD17 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD17 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD17_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD17_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD18 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD18_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD18_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD19 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD19 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD19_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD19_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD20 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD20 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD20_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD20_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD21 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD21 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD21_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD21_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD22 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD22 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD22_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD22_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD23 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD23 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD23_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MEMINTD23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD16 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD16_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD16_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD17 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD17 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD17_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD17_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD18 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD18_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD18_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD19 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD19 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD19_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD19_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD20 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD20 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD20_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD20_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD21 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD21 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD21_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD21_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD22 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD22 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD22_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD22_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD23 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD23 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD23_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD16 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD16_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD16_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD17 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD17 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD17_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD17_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD18 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD18_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD18_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD19 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD19 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD19_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD19_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD20 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD20 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD20_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD20_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD21 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD21 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD21_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD21_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD22 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD22 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD22_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD22_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD23 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD23 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD23_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MEMINTD23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD16 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD16_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD16_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD17 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD17 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD17_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD17_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD18 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD18_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD18_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD19 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD19 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD19_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD19_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD20 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD20 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD20_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD20_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD21 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD21 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD21_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD21_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD22 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD22 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD22_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD22_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD23 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD23 ); +REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD23_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MEMINTD23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_DQSCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_RDCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_DQSCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_RDCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_DQSCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_RDCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_DQSCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_RDCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SYSCLK_DQSCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SYSCLK_RDCLK_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_SM ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_SM_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_ITR_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_ITR_CNTR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_SM ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_SM_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_ITR_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DQS_ALIGN_ITR_CNTR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_SM ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_SM_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_ITR_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_ITR_CNTR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_SM ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_SM_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_ITR_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DQS_ALIGN_ITR_CNTR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_DQS_ALIGN_SM ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_DQS_ALIGN_SM_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_DQS_ALIGN_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_DQS_ALIGN_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_DQS_ALIGN_ITR_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_DQS_ALIGN_ITR_CNTR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CALIBRATE_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CALIBRATE_BIT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_ALIGN_QUAD ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_OPERATE_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_OPERATE_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_EN_DQS_OFFSET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_EN_DQS_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_JITTER , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_ALIGN_JITTER ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DIS_CLK_GATE , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DIS_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_MAX_DQS_ITER , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_MAX_DQS_ITER ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CALIBRATE_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_CALIBRATE_BIT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_ALIGN_QUAD ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_OPERATE_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_OPERATE_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_EN_DQS_OFFSET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_EN_DQS_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_JITTER , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_ALIGN_JITTER ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DIS_CLK_GATE , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DIS_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_MAX_DQS_ITER , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_MAX_DQS_ITER ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CALIBRATE_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CALIBRATE_BIT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_ALIGN_QUAD ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_OPERATE_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_OPERATE_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_EN_DQS_OFFSET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_EN_DQS_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_JITTER , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_ALIGN_JITTER ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DIS_CLK_GATE , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DIS_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_MAX_DQS_ITER , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_MAX_DQS_ITER ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CALIBRATE_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_CALIBRATE_BIT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_ALIGN_QUAD ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_OPERATE_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_OPERATE_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_EN_DQS_OFFSET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_EN_DQS_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_JITTER , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_ALIGN_JITTER ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DIS_CLK_GATE , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DIS_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_MAX_DQS_ITER , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_MAX_DQS_ITER ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CALIBRATE_BIT ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_CALIBRATE_BIT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD , 51 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DQS_ALIGN_QUAD ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_OPERATE_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_OPERATE_MODE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_EN_DQS_OFFSET , 60 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_EN_DQS_OFFSET ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_JITTER , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DQS_ALIGN_JITTER ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DIS_CLK_GATE , 62 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DIS_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_MAX_DQS_ITER , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_MAX_DQS_ITER ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW , 56 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0_01_DQS_ALIGN_FIX_DIS , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_ALIGN_FIX_DIS ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1_01_DQS_ALIGN_FIX_DIS , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_ALIGN_FIX_DIS ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2_23_DQS_ALIGN_FIX_DIS , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_ALIGN_FIX_DIS ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3_23_DQS_ALIGN_FIX_DIS , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_ALIGN_FIX_DIS ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4_4_DQS_ALIGN_FIX_DIS , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DQS_ALIGN_FIX_DIS ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_POWER_CNTL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DYN_POWER_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_MCTERM_CNTL_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DYN_MCTERM_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_RX_GATE_CNTL_EN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DYN_RX_GATE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CALGATE_ON , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CALGATE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PER_CAL_UPDATE_DISABLE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PER_CAL_UPDATE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_PIPE_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_PIPE_FIX_DIS_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DD2_DQS_FIX_DIS , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_DQS_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DL_FORCE_ON , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DL_FORCE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_BLFIFO_DIS , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BLFIFO_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_WTRFL_AVE_DIS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WTRFL_AVE_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PERCAL_PWR_DIS , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PERCAL_PWR_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_FIX_EN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LOOPBACK_FIX_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_DLY12 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LOOPBACK_DLY12 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DD2_WTRFL_SYNC_DIS , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_WTRFL_SYNC_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_FORCE_FIFO_CAPTURE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FORCE_FIFO_CAPTURE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_POWER_CNTL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DYN_POWER_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_MCTERM_CNTL_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DYN_MCTERM_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_RX_GATE_CNTL_EN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DYN_RX_GATE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CALGATE_ON , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CALGATE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PER_CAL_UPDATE_DISABLE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PER_CAL_UPDATE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_PIPE_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DQS_PIPE_FIX_DIS_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DD2_DQS_FIX_DIS , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_DQS_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DL_FORCE_ON , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DL_FORCE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_BLFIFO_DIS , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_BLFIFO_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_WTRFL_AVE_DIS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WTRFL_AVE_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PERCAL_PWR_DIS , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PERCAL_PWR_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_FIX_EN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LOOPBACK_FIX_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_DLY12 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LOOPBACK_DLY12 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DD2_WTRFL_SYNC_DIS , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_WTRFL_SYNC_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_FORCE_FIFO_CAPTURE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FORCE_FIFO_CAPTURE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_POWER_CNTL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DYN_POWER_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_MCTERM_CNTL_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DYN_MCTERM_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_RX_GATE_CNTL_EN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DYN_RX_GATE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CALGATE_ON , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CALGATE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PER_CAL_UPDATE_DISABLE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PER_CAL_UPDATE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_PIPE_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_PIPE_FIX_DIS_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DD2_DQS_FIX_DIS , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DD2_DQS_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DL_FORCE_ON , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DL_FORCE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_BLFIFO_DIS , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BLFIFO_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_WTRFL_AVE_DIS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WTRFL_AVE_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PERCAL_PWR_DIS , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PERCAL_PWR_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_FIX_EN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LOOPBACK_FIX_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_DLY12 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LOOPBACK_DLY12 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DD2_WTRFL_SYNC_DIS , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DD2_WTRFL_SYNC_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_FORCE_FIFO_CAPTURE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FORCE_FIFO_CAPTURE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_POWER_CNTL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DYN_POWER_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_MCTERM_CNTL_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DYN_MCTERM_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_RX_GATE_CNTL_EN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DYN_RX_GATE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CALGATE_ON , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CALGATE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PER_CAL_UPDATE_DISABLE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PER_CAL_UPDATE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_PIPE_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DQS_PIPE_FIX_DIS_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DD2_DQS_FIX_DIS , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DD2_DQS_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DL_FORCE_ON , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DL_FORCE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_BLFIFO_DIS , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_BLFIFO_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_WTRFL_AVE_DIS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WTRFL_AVE_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PERCAL_PWR_DIS , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PERCAL_PWR_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_FIX_EN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LOOPBACK_FIX_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_DLY12 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LOOPBACK_DLY12 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DD2_WTRFL_SYNC_DIS , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DD2_WTRFL_SYNC_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_FORCE_FIFO_CAPTURE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FORCE_FIFO_CAPTURE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_POWER_CNTL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DYN_POWER_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_MCTERM_CNTL_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DYN_MCTERM_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_RX_GATE_CNTL_EN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DYN_RX_GATE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CALGATE_ON , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CALGATE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PER_CAL_UPDATE_DISABLE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PER_CAL_UPDATE_DISABLE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DQS_PIPE_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DQS_PIPE_FIX_DIS_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DD2_DQS_FIX_DIS , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DD2_DQS_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DL_FORCE_ON , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DL_FORCE_ON ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_BLFIFO_DIS , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_BLFIFO_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_WTRFL_AVE_DIS , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WTRFL_AVE_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PERCAL_PWR_DIS , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PERCAL_PWR_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_FIX_EN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LOOPBACK_FIX_EN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_DLY12 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LOOPBACK_DLY12 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DD2_WTRFL_SYNC_DIS , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DD2_WTRFL_SYNC_DIS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_FORCE_FIFO_CAPTURE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_FORCE_FIFO_CAPTURE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_EYE_DETECTED_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_EYE_DETECTED_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_LEADING_EDGE_FOUND_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEADING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_TRAILING_EDGE_FOUND_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TRAILING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N0_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N1_MASK , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N2_MASK , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N3_MASK , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N0_MASK , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N1_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N2_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N3_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_EYE_CLIPPING_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EYE_CLIPPING_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_DQS_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_DQS_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_LOCK_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_LOCK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_DRIFT_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRIFT_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_MIN_EYE_MASK , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_EYE_MASK ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_EYE_DETECTED_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_EYE_DETECTED_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_LEADING_EDGE_FOUND_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEADING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_TRAILING_EDGE_FOUND_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TRAILING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N0_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N1_MASK , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N2_MASK , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N3_MASK , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N0_MASK , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N1_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N2_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N3_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_EYE_CLIPPING_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EYE_CLIPPING_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_DQS_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_DQS_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_LOCK_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_LOCK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_DRIFT_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRIFT_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_MIN_EYE_MASK , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_EYE_MASK ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_EYE_DETECTED_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_EYE_DETECTED_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_LEADING_EDGE_FOUND_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEADING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_TRAILING_EDGE_FOUND_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TRAILING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N0_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N1_MASK , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N2_MASK , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N3_MASK , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N0_MASK , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N1_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N2_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N3_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_EYE_CLIPPING_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EYE_CLIPPING_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_DQS_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_DQS_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_LOCK_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_LOCK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_DRIFT_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRIFT_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_MIN_EYE_MASK , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_EYE_MASK ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_EYE_DETECTED_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_EYE_DETECTED_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_LEADING_EDGE_FOUND_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEADING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_TRAILING_EDGE_FOUND_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TRAILING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N0_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N1_MASK , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N2_MASK , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N3_MASK , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N0_MASK , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N1_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N2_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N3_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_EYE_CLIPPING_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EYE_CLIPPING_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_DQS_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_DQS_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_LOCK_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_LOCK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_DRIFT_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRIFT_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_MIN_EYE_MASK , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_EYE_MASK ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_EYE_DETECTED_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_EYE_DETECTED_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_LEADING_EDGE_FOUND_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEADING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_TRAILING_EDGE_FOUND_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_TRAILING_EDGE_FOUND_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N0_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N1_MASK , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N2_MASK , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N3_MASK , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N0_MASK , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N1_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N2_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N3_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_EYE_CLIPPING_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EYE_CLIPPING_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_DQS_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_DQS_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_LOCK_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_LOCK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_DRIFT_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DRIFT_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_MIN_EYE_MASK , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_EYE_MASK ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_LEADING_EDGE_NOT_FOUND_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_LEADING_EDGE_NOT_FOUND_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_0_01_LEADING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_0_01_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_1_01_LEADING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_1_01_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_2_23_LEADING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_2_23_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_3_23_LEADING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_3_23_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_4_4_LEADING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_4_4_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_0_01_TRAILING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_0_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_1_01_TRAILING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_1_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_2_23_TRAILING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_2_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_3_23_TRAILING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_3_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_4_4_TRAILING_EDGE_NOT_FOUND_16_23 , 48 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_4_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8 , SH_UNT_MCA , + SH_ACS_SCOM_RO , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_EYE_DETECTED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_EYE_DETECTED ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEADING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_TRAILING_EDGE_NOT_FOUND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TRAILING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_EYE_CLIPPING , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EYE_CLIPPING ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_DQS , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_LOCK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_LOCK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_DRIFT_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRIFT_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_MIN_EYE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_EYE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_EYE_DETECTED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_EYE_DETECTED ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEADING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_TRAILING_EDGE_NOT_FOUND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TRAILING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INCOMPLETE_CAL_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_COARSE_PATTERN_ERR_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_EYE_CLIPPING , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EYE_CLIPPING ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_DQS , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_LOCK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NO_LOCK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_DRIFT_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRIFT_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_MIN_EYE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_MIN_EYE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_EYE_DETECTED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_EYE_DETECTED ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEADING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_TRAILING_EDGE_NOT_FOUND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TRAILING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_EYE_CLIPPING , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EYE_CLIPPING ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_DQS , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_LOCK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_LOCK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_DRIFT_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRIFT_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_MIN_EYE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_EYE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_EYE_DETECTED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_EYE_DETECTED ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEADING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_TRAILING_EDGE_NOT_FOUND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TRAILING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INCOMPLETE_CAL_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_COARSE_PATTERN_ERR_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_EYE_CLIPPING , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EYE_CLIPPING ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_DQS , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_LOCK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NO_LOCK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_DRIFT_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRIFT_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_MIN_EYE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_MIN_EYE ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_EYE_DETECTED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_EYE_DETECTED ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEADING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_TRAILING_EDGE_NOT_FOUND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_TRAILING_EDGE_NOT_FOUND ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N0 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N1 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INCOMPLETE_CAL_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N0 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_COARSE_PATTERN_ERR_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_EYE_CLIPPING , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EYE_CLIPPING ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_DQS , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_DQS ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_LOCK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NO_LOCK ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_DRIFT_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DRIFT_ERROR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_MIN_EYE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_MIN_EYE ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_DELAY6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE5_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE6_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RD_SIZE7_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REFERENCE1 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REFERENCE1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_REFERENCE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_REFERENCE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REFERENCE2 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REFERENCE2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REFERENCE3 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_REFERENCE3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB0TCFLIP_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB1TCFLIP_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB2TCFLIP_DC , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB3TCFLIP_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_DISABLE_TERMINATION , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_TERMINATION ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_READ_CENTERING_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_READ_CENTERING_MODE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB0TCFLIP_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB1TCFLIP_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB2TCFLIP_DC , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB3TCFLIP_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_DISABLE_TERMINATION , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DISABLE_TERMINATION ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_READ_CENTERING_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_READ_CENTERING_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_READ_CENTERING_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_READ_CENTERING_MODE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB0TCFLIP_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB1TCFLIP_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB2TCFLIP_DC , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB3TCFLIP_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_DISABLE_TERMINATION , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_TERMINATION ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_READ_CENTERING_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_READ_CENTERING_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_READ_CENTERING_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_READ_CENTERING_MODE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB0TCFLIP_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB1TCFLIP_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB2TCFLIP_DC , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB3TCFLIP_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_DISABLE_TERMINATION , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DISABLE_TERMINATION ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_READ_CENTERING_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_READ_CENTERING_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_READ_CENTERING_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_READ_CENTERING_MODE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB0TCFLIP_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB0TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB1TCFLIP_DC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB1TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB2TCFLIP_DC , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB2TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB3TCFLIP_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB3TCFLIP_DC ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_DISABLE_TERMINATION , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DISABLE_TERMINATION ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_READ_CENTERING_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_READ_CENTERING_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_READ_CENTERING_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_READ_CENTERING_MODE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ENABLE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_OVERRIDE_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ROT_OVERRIDE_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_ALIGN_RESET , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PHASE_ALIGN_RESET ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_CNTL_EN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PHASE_CNTL_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_DEFAULT_EN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_PHASE_DEFAULT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_POS_EDGE_ALIGN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_POS_EDGE_ALIGN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CONTINUOUS_UPDATE ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BB_LOCK0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BB_LOCK1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BB_LOCK0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BB_LOCK1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ROT1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BB_LOCK0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BB_LOCK1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BB_LOCK0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BB_LOCK1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ROT1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BB_LOCK0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT0 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BB_LOCK1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT1 ); +REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ROT1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_0_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_0_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_1_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_1_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_2_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_2_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_3_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_3_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_4_4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_4_4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_0_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_0_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_1_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_1_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_2_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_2_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_3_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_3_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_4_4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_4_4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK16 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK16 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK18 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD0_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD1_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK20 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK22 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK22 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK16_SINGLE_ENDED , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK16_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK18_SINGLE_ENDED , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK18_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK20_SINGLE_ENDED , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK20_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK22_SINGLE_ENDED , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK22_SINGLE_ENDED ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK18 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD2_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK18 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_QUAD3_CLK18 ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TSYS ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TSYS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TSYS ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_TSYS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TSYS ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TSYS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TSYS ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_TSYS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_TSYS ); +REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_TSYS_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_CENTERED ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_CENTERED_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_LEFT , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_SMALL_STEP_LEFT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIG_STEP_RIGHT , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIG_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_MATCH_STEP_RIGHT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MATCH_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_JUMP_BACK_RIGHT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_JUMP_BACK_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_RIGHT , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_SMALL_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_DONE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DONE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_CENTERED ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIT_CENTERED_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_LEFT , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_SMALL_STEP_LEFT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIG_STEP_RIGHT , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_BIG_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_MATCH_STEP_RIGHT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_MATCH_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_JUMP_BACK_RIGHT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_JUMP_BACK_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_RIGHT , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_SMALL_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_DONE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_DONE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_CENTERED ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_CENTERED_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_LEFT , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_SMALL_STEP_LEFT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIG_STEP_RIGHT , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIG_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_MATCH_STEP_RIGHT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MATCH_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_JUMP_BACK_RIGHT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_JUMP_BACK_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_RIGHT , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_SMALL_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_DONE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DONE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_CENTERED ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIT_CENTERED_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_LEFT , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_SMALL_STEP_LEFT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIG_STEP_RIGHT , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_BIG_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_MATCH_STEP_RIGHT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_MATCH_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_JUMP_BACK_RIGHT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_JUMP_BACK_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_RIGHT , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_SMALL_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_DONE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_DONE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BIT_CENTERED ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BIT_CENTERED_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_LEFT , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_SMALL_STEP_LEFT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIG_STEP_RIGHT , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_BIG_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_MATCH_STEP_RIGHT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_MATCH_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_JUMP_BACK_RIGHT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_JUMP_BACK_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_RIGHT , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_SMALL_STEP_RIGHT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_DONE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_DONE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_LEFT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_LEFT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_LEFT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_LEFT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_LEFT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_LEFT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_LEFT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_LEFT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_FW_LEFT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_FW_LEFT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_RIGHT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_RIGHT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_RIGHT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_FW_RIGHT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_RIGHT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_RIGHT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_RIGHT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_FW_RIGHT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_FW_RIGHT_SIDE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_FW_RIGHT_SIDE_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK18 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK20 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK22 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_L , 56 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_VALID_NS_BIG_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_L , 57 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_INVALID_NS_SMALL_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_R , 58 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_VALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_BIG_R , 59 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_INVALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_JUMP_BACK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_VALID_NS_JUMP_BACK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_R , 61 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_INVALID_NS_SMALL_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_OFFSET_ERR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_OFFSET_ERR ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK18 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK20 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK22 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_L , 56 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_VALID_NS_BIG_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_L , 57 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_INVALID_NS_SMALL_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_R , 58 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_VALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_BIG_R , 59 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_INVALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_JUMP_BACK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_VALID_NS_JUMP_BACK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_R , 61 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_INVALID_NS_SMALL_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_OFFSET_ERR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_01_OFFSET_ERR ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK18 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK20 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK22 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_L , 56 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_VALID_NS_BIG_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_L , 57 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_INVALID_NS_SMALL_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_R , 58 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_VALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_BIG_R , 59 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_INVALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_JUMP_BACK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_VALID_NS_JUMP_BACK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_R , 61 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_INVALID_NS_SMALL_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_OFFSET_ERR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_OFFSET_ERR ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK18 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK20 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK22 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_L , 56 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_VALID_NS_BIG_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_L , 57 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_INVALID_NS_SMALL_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_R , 58 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_VALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_BIG_R , 59 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_INVALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_JUMP_BACK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_VALID_NS_JUMP_BACK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_R , 61 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_INVALID_NS_SMALL_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_OFFSET_ERR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_23_OFFSET_ERR ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK18 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK20 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK22 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_L , 56 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_VALID_NS_BIG_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_L , 57 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_INVALID_NS_SMALL_L ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_R , 58 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_VALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_BIG_R , 59 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_INVALID_NS_BIG_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_JUMP_BACK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_VALID_NS_JUMP_BACK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_R , 61 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_INVALID_NS_SMALL_R ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_OFFSET_ERR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RCLRPART, + SH_FLD_4_OFFSET_ERR ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK16_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK16_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK18_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK18_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK20_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK20_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ERR_CLK22_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ERR_CLK22_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_L_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALID_NS_BIG_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_L_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INVALID_NS_SMALL_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_R_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_BIG_R_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INVALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_JUMP_BACK_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALID_NS_JUMP_BACK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_R_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INVALID_NS_SMALL_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_OFFSET_ERR_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET_ERR_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ADVANCE_PR_VALUE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ADVANCE_PR_VALUE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK16_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK16_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK18_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK18_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK20_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK20_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ERR_CLK22_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ERR_CLK22_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_L_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALID_NS_BIG_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_L_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INVALID_NS_SMALL_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_R_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_BIG_R_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INVALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_JUMP_BACK_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALID_NS_JUMP_BACK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_R_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_INVALID_NS_SMALL_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_OFFSET_ERR_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_OFFSET_ERR_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ADVANCE_PR_VALUE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ADVANCE_PR_VALUE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK16_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK16_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK18_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK18_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK20_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK20_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ERR_CLK22_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ERR_CLK22_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_L_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALID_NS_BIG_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_L_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INVALID_NS_SMALL_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_R_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_BIG_R_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INVALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_JUMP_BACK_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALID_NS_JUMP_BACK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_R_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INVALID_NS_SMALL_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_OFFSET_ERR_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET_ERR_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ADVANCE_PR_VALUE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ADVANCE_PR_VALUE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK16_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK16_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK18_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK18_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK20_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK20_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ERR_CLK22_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ERR_CLK22_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_L_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALID_NS_BIG_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_L_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INVALID_NS_SMALL_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_R_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_BIG_R_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INVALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_JUMP_BACK_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALID_NS_JUMP_BACK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_R_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_INVALID_NS_SMALL_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_OFFSET_ERR_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_OFFSET_ERR_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ADVANCE_PR_VALUE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ADVANCE_PR_VALUE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK16_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ERR_CLK16_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK18_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ERR_CLK18_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK20_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ERR_CLK20_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ERR_CLK22_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ERR_CLK22_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_L_MASK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALID_NS_BIG_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_L_MASK , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INVALID_NS_SMALL_L_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_R_MASK , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_BIG_R_MASK , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INVALID_NS_BIG_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_JUMP_BACK_MASK , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALID_NS_JUMP_BACK_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_R_MASK , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_INVALID_NS_SMALL_R_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_OFFSET_ERR_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_OFFSET_ERR_MASK ); +REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ADVANCE_PR_VALUE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ADVANCE_PR_VALUE ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK_LEVEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK_LEVEL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_FINE_STEPPING , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FINE_STEPPING ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_DONE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DONE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK16 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK22 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_ZERO_DETECTED , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ZERO_DETECTED ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK_LEVEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CLK_LEVEL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_FINE_STEPPING , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_FINE_STEPPING ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_DONE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DONE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK16 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK22 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_ZERO_DETECTED , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ZERO_DETECTED ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK_LEVEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK_LEVEL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_FINE_STEPPING , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FINE_STEPPING ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_DONE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DONE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK16 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK22 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_ZERO_DETECTED , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ZERO_DETECTED ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK_LEVEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CLK_LEVEL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_FINE_STEPPING , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_FINE_STEPPING ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_DONE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DONE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK16 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK22 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_ZERO_DETECTED , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ZERO_DETECTED ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK_LEVEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CLK_LEVEL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_FINE_STEPPING , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_FINE_STEPPING ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_DONE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DONE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK16 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ERR_CLK16 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK18 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ERR_CLK18 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK20 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ERR_CLK20 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK22 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_WL_ERR_CLK22 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_ZERO_DETECTED , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ZERO_DETECTED ); + +REG64_FLD( MCA_DDRPHY_PC_ADR_DLL_CAL_STATUS_P0_GOOD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_GOOD ); +REG64_FLD( MCA_DDRPHY_PC_ADR_DLL_CAL_STATUS_P0_ERROR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERROR ); +REG64_FLD( MCA_DDRPHY_PC_ADR_DLL_CAL_STATUS_P0_ERROR_FINE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC ); +REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC ); +REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC ); +REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERIODIC ); +REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERIODIC_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PROTOCOL ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PROTOCOL_LEN ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DATA_MUX4_1MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DATA_MUX4_1MODE ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_SPAM_EN , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SPAM_EN ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR4_CMD_SIG_REDUCTION ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_SYSCLK_2X_MEMINTCLKO , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SYSCLK_2X_MEMINTCLKO ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RANK_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RANK_OVERRIDE_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RANK_OVERRIDE_VALUE_LEN ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_LOW_LATENCY , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_LOW_LATENCY ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR4_IPW_LOOP_DIS ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR4_VLEVEL_BANK_GROUP ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_ZCAL_NOT_CONT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ZCAL_NOT_CONT ); + +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRITE_LATENCY_OFFSET ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRITE_LATENCY_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_READ_LATENCY_OFFSET ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_READ_LATENCY_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CIC_FAST , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MEMCTL_CIC_FAST ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CTRN_IGNORE , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MEMCTL_CTRN_IGNORE ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_DISABLE_MEMCTL_CAL , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_MEMCTL_CAL ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MEMORY_TYPE ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MEMORY_TYPE_LEN ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR4_LATENCY_SW ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_RETRAIN_PERCAL_SW , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RETRAIN_PERCAL_SW ); + +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS0_INIT_CAL_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS0_INIT_CAL_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS1_INIT_CAL_VALUE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS1_INIT_CAL_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS2_INIT_CAL_VALUE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS2_INIT_CAL_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS3_INIT_CAL_VALUE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS3_INIT_CAL_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS4_INIT_CAL_VALUE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS4_INIT_CAL_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS5_INIT_CAL_VALUE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS5_INIT_CAL_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS6_INIT_CAL_VALUE , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS6_INIT_CAL_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS7_INIT_CAL_VALUE , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CS7_INIT_CAL_VALUE ); + +REG64_FLD( MCA_DDRPHY_PC_DP16_DLL_CAL_STATUS_P0_DP_GOOD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DP_GOOD ); +REG64_FLD( MCA_DDRPHY_PC_DP16_DLL_CAL_STATUS_P0_DP_ERROR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DP_ERROR ); +REG64_FLD( MCA_DDRPHY_PC_DP16_DLL_CAL_STATUS_P0_DP_ERROR_FINE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DP_ERROR_FINE ); + +REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_RC_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RC_MASK ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_WC_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WC_MASK ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_SEQ_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEQ_MASK ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_CC_MASK , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CC_MASK ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_APB_MASK , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_APB_MASK ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_MASK , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MASK ); + +REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_RC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RC ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_WC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WC ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_SEQ , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_SEQ ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_CC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CC ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_APB , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_APB ); +REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_ERROR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERROR ); + +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WR_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_WR_LEVEL ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_PAT_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_INITIAL_PAT_WR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DQS_ALIGN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_DQS_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RDCLK_ALIGN , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RDCLK_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_READ_CTR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_READ_CTR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WRITE_CTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_WRITE_CTR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_COARSE_WR , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_INITIAL_COARSE_WR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_COARSE_RD , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_COARSE_RD ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_CUSTOM_RD ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_CUSTOM_WR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ABORT_ON_ERROR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DIGITAL_EYE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_DIGITAL_EYE ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RANK_PAIR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RANK_PAIR_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_COUNT ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_COUNT_LEN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_CONTROL ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_CONTROL_LEN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_ALL_RANKS , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_ALL_RANKS ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_SNOOP_DIS , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SNOOP_DIS ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_INTERVAL ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_INTERVAL_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WR_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WR_LEVEL ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_PAT_WRITE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_INITIAL_PAT_WRITE ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DQS_ALIGN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DQS_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RDCLK_ALIGN , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RDCLK_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_READ_CTR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_READ_CTR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WRITE_CTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRITE_CTR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_COARSE_WR , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_INITIAL_COARSE_WR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_COARSE_RD , 55 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_COARSE_RD ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CUSTOM_RD ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CUSTOM_WR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DIGITAL_EYE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DIGITAL_EYE ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RANK_PAIR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RANK_PAIR_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WR_LEVEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_WR_LEVEL ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_PAT_WRITE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INITIAL_PAT_WRITE ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DQS_ALIGN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_DQS_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_RDCLK_ALIGN , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_RDCLK_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_READ_CTR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_READ_CTR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WRITE_CTR , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_WRITE_CTR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_COARSE_WR , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INITIAL_COARSE_WR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_COARSE_RD , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_COARSE_RD ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_RD , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CUSTOM_RD ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CUSTOM_WR ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DIGITAL_EYE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ERROR_DIGITAL_EYE ); + +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_COMPLETE ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_COMPLETE_LEN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_52_56 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_52_56 ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_52_56_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_52_56_LEN ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_PER_ABORT , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PER_ABORT ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_58_63 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_58_63 ); +REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_58_63_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_58_63_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PVTP ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTP_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PVTP_LEN ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTN , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PVTN ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTN_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PVTN_LEN ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_OVERRIDE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_ENABLE_ZCAL , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_ZCAL ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_RESET_ZCAL , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESET_ZCAL ); + +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PVTP ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTP_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PVTP_LEN ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTN , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PVTN ); +REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTN_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PVTN_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP0_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP0_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP1_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP1_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP2_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP2_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP3_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP3_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP0_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP0_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP1_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP1_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP2_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP2_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP3_P0_MODE_REGISTER_0_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP3_P0_MODE_REGISTER_0_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_0_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP0_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP0_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP1_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP1_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP2_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP2_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP3_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP3_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP0_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP0_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP1_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP1_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP2_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP2_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP3_P0_MODE_REGISTER_1_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP3_P0_MODE_REGISTER_1_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_1_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP0_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP0_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP1_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP1_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP2_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP2_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP3_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP3_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP0_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP0_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP1_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP1_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP2_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP2_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP3_P0_MODE_REGISTER_2_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP3_P0_MODE_REGISTER_2_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_2_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP0_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP0_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP1_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP1_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP2_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP2_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP3_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP3_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP0_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP0_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP1_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP1_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP2_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP2_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP3_P0_MODE_REGISTER_3_VALUE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE ); +REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP3_P0_MODE_REGISTER_3_VALUE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MODE_REGISTER_3_VALUE_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RANK_PAIR ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RANK_PAIR_LEN ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_ZCAL , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_ZCAL ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_SYSCLK_ALIGN , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_SYSCLK_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_READ_CTR , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_READ_CTR ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RDCLK_ALIGN , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RDCLK_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_DQS_ALIGN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_DQS_ALIGN ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NEXT_RANK_PAIR ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NEXT_RANK_PAIR_LEN ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_FAST_SIM_CNTR , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FAST_SIM_CNTR ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START_INIT , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_START_INIT ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_START ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ABORT_ON_ERR_EN , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ABORT_ON_ERR_EN ); +REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_DD2_FIX_DIS , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DD2_FIX_DIS ); + +REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RANK ); +REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ENA_RANK_LEN ); +REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NEXT_RANK ); +REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NEXT_RANK_LEN ); +REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_START , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_START ); + +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_MASTER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MASTER ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DLL ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL_CLOCK_GATE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DLL_CLOCK_GATE ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_OUTPUT_STAB , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ANALOG_OUTPUT_STAB ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB1 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ANALOG_INPUT_STAB1 ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_SYSCLK_CLK_GATE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SYSCLK_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DELAY_LINE_CTL_OVERRIDE , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAY_LINE_CTL_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_WR_FIFO_STAB , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WR_FIFO_STAB ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DP16_RX_PD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DP16_RX_PD ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DP16_RX_PD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DP16_RX_PD_LEN ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_TX_TRISTATE_CNTL , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TX_TRISTATE_CNTL ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_VCC_REG_PD , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VCC_REG_PD ); + +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_TER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP0_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_QUA , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP0_QUA ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_TER , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP1_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_QUA , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP1_QUA ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_TER , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP2_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_QUA , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP2_QUA ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_TER , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP3_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_QUA , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP3_QUA ); + +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP0_PRI , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP0_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP0_SEC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP0_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP1_PRI , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP1_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP1_SEC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP1_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP2_PRI , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP2_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP2_SEC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP2_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP3_PRI , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP3_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP3_SEC , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_RP3_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_GROUPING , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_GROUPING ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_GROUPING_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_GROUPING_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A3_A4 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_A3_A4 ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A5_A6 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_A5_A6 ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A7_A8 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_A7_A8 ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A11_A13 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_A11_A13 ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_BA0_BA1 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_BA0_BA1 ); +REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_BG0_BG1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR_MIRROR_BG0_BG1 ); + +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PRI_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_V , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PRI_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEC_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_V , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEC_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_PRI_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_V , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_PRI_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_SEC_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_V , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_SEC_V ); + +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_PRI_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_V , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_PRI_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_SEC_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_V , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_SEC_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR3_PRI ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR3_PRI_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_V , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR3_PRI_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR3_SEC ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR3_SEC_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_V , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR3_SEC_V ); + +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR0_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR0_TER_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_V , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR0_TER_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR0_QUA ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR0_QUA_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_V , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR0_QUA_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_TER_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_V , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_TER_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_QUA ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_QUA_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_V , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR1_QUA_V ); + +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_TER_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_V , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_TER_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_QUA ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_QUA_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_V , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAIR2_QUA_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_TER , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TER ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TER_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_V , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TER_V ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_QUA ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_QUA_LEN ); +REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_V , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_QUA_V ); + +REG64_FLD( MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_CAL_REQ_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERIODIC_CAL_REQ_EN ); +REG64_FLD( MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERIODIC ); +REG64_FLD( MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERIODIC_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SYSCLK_RESET ); + +REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0DSGN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VREFDQ0DSGN ); +REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0D , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VREFDQ0D ); +REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0D_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VREFDQ0D_LEN ); +REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1DSGN , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VREFDQ1DSGN ); +REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1D , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VREFDQ1D ); +REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1D_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VREFDQ1D_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC ); +REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PERIODIC_LEN ); + +REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERIODIC ); +REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERIODIC_LEN ); + +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_GLOBAL_PHY_OFFSET ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_GLOBAL_PHY_OFFSET_LEN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_ADVANCE_RD_VALID , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADVANCE_RD_VALID ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PER_DUTY_CYCLE_SW , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PER_DUTY_CYCLE_SW ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PER_REPEAT_COUNT ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PER_REPEAT_COUNT_LEN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP0 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SINGLE_BIT_MPR_RP0 ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SINGLE_BIT_MPR_RP1 ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP2 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SINGLE_BIT_MPR_RP2 ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP3 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SINGLE_BIT_MPR_RP3 ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_ALIGN_ON_EVEN_CYCLES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ALIGN_ON_EVEN_CYCLES ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PERFORM_RDCLK_ALIGN , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERFORM_RDCLK_ALIGN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_STAGGERED_PATTERN , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_STAGGERED_PATTERN ); + +REG64_FLD( MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_OUTER_LOOP_CNT ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT_LEN , 14 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_OUTER_LOOP_CNT_LEN ); + +REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_CONSEQ_PASS , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONSEQ_PASS ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_CONSEQ_PASS_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONSEQ_PASS_LEN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_BURST_WINDOW , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_BURST_WINDOW ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_BURST_WINDOW_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_BURST_WINDOW_LEN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_ALLOW_RD_FIFO_AUTO_RESET , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ALLOW_RD_FIFO_AUTO_RESET ); + +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FINE_CAL_STEP_SIZE ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FINE_CAL_STEP_SIZE_LEN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_COARSE_CAL_STEP_SIZE ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_COARSE_CAL_STEP_SIZE_LEN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DQ_SEL_QUAD ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DQ_SEL_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DQ_SEL_LANE ); +REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DQ_SEL_LANE_LEN ); + +REG64_FLD( MCA_DDRPHY_RC_ERROR_MASK0_P0_RD_CNTL_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RD_CNTL_MASK ); + +REG64_FLD( MCA_DDRPHY_RC_ERROR_STATUS0_P0_RD_CNTL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RD_CNTL ); + +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_MPR_PATTERN_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MPR_PATTERN_BIT ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_TWO_CYCLE_ADDR_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TWO_CYCLE_ADDR_EN ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MR_MASK_EN ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MR_MASK_EN_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_DELAYED_PAR , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYED_PAR ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_LRDIMM_CONTEXT , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_CONTEXT ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_FORCE_RESERVED , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FORCE_RESERVED ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_HALT_ROTATION , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_HALT_ROTATION ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_FORCE_MPR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FORCE_MPR ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_CLONE_CS_MODE , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CLONE_CS_MODE ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_INVERT , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAR_INVERT ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_IPW_SIDEAB_SEL , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_IPW_SIDEAB_SEL ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_17_MASK , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PAR_17_MASK ); +REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_CW_MIRROR , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CW_MIRROR ); + +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_MASK0_P0_MULT_REQ_ERR_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MULT_REQ_ERR_MASK ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_MASK0_P0_INVALID_REQTYPE_ERR_MASK , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INVALID_REQTYPE_ERR_MASK ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_MASK0_P0_EARLY_REQ_ERR_MASK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EARLY_REQ_ERR_MASK ); + +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_MULTIPLE_REQ ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EARLY_REQ ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_MULTIPLE_REQ_SOURCE ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_MULTIPLE_REQ_SOURCE_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_INVALID_REQTYPE ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_INVALID_REQTYPE_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_INVALID_REQ_SOURCE ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_INVALID_REQ_SOURCE_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EARLY_REQ_SOURCE ); +REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EARLY_REQ_SOURCE_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR2 ); +REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR2_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR3 ); +REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR3_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR4 ); +REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR4_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TMOD_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TMOD_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRCD_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRCD_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRP_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRP_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRFC_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRFC_CYCLES_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TZQINIT_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TZQINIT_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TZQCS_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TZQCS_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TWLDQSEN_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TWLDQSEN_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TWRMRD_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TWRMRD_CYCLES_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TODTLON_OFF_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TODTLON_OFF_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRC_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRC_CYCLES_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TMRSC_CYCLES ); +REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TMRSC_CYCLES_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P0_DEF_VALUES , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DEF_VALUES ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P0_DEF_VALUES_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DEF_VALUES_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES0 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES0_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES1 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES1_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES2_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES3_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES4 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES4_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES4_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES5 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES5_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES6 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES6_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES6_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES7 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES7_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES0 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES0_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES1 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES1_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES2_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES3_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES4 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES4_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES4_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES5 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES5_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES6 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES6 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES6_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES6_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES7 ); +REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VALUES7_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DATA_REG0 ); +REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DATA_REG0_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DATA_REG1 ); +REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DATA_REG1_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR0 ); +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR0_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR1 ); +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR1_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR2 ); +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR2_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR3 ); +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR3_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR4 ); +REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDR4_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_0_2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_0_2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_0_2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_TYPE_0_2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_0_2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_0_2_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_1_3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_1_3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_1_3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_TYPE_1_3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_1_3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_1_3_LEN ); + +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_0_2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_0_2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_0_2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_TYPE_0_2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_0_2 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_0_2_LEN ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_1_3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_1_3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_1_3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_TYPE_1_3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_1_3 ); +REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEL_1_3_LEN ); + +REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TWLO_TWLOE ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TWLO_TWLOE_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_WL_ONE_DQS_PULSE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WL_ONE_DQS_PULSE ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FW_WR_RD ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FW_WR_RD_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_CUSTOM_INIT_WRITE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CUSTOM_INIT_WRITE ); + +REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_BIG_STEP ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_BIG_STEP_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SMALL_STEP ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SMALL_STEP_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WR_PRE_DLY ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WR_PRE_DLY_LEN ); + +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NUM_VALID_SAMPLES ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NUM_VALID_SAMPLES_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FW_RD_WR ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FW_RD_WR_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_IPW_WR_WR ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_IPW_WR_WR_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_DD2_FIX_DIS , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EN_RESET_DD2_FIX_DIS ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EN_RESET_WR_DELAY_WL ); + +REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_DDR4_MRS_CMD_DQ_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR4_MRS_CMD_DQ_EN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MRS_CMD_DQ_ON ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MRS_CMD_DQ_ON_LEN ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MRS_CMD_DQ_OFF ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MRS_CMD_DQ_OFF_LEN ); + +REG64_FLD( MCA_DDRPHY_WC_ERROR_MASK0_P0_WR_CNTL_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WR_CNTL_MASK ); + +REG64_FLD( MCA_DDRPHY_WC_ERROR_STATUS0_P0_WR_CNTL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WR_CNTL ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3_23_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3_23_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DELAYG_LEN ); + +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4_4_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG ); +REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4_4_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DELAYG_LEN ); + +REG64_FLD( MCA_EICR_ADDRESS , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_EICR_ADDRESS_LEN , 37 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_EICR_RESERVED , 37 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED ); +REG64_FLD( MCA_EICR_PERSIST , 38 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERSIST ); +REG64_FLD( MCA_EICR_PERSIST_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PERSIST_LEN ); +REG64_FLD( MCA_EICR_REGION , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_EICR_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_EICR_TYPE , 43 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_EICR_TYPE_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE_LEN ); +REG64_FLD( MCA_EICR_MISC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MISC ); +REG64_FLD( MCA_EICR_MISC_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MISC_LEN ); + +REG64_FLD( MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7 , 0 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_MPE_RANK_0_TO_7 ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_NCE , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_NCE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_TCE , 9 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_TCE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_SCE , 10 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_SCE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_MCE , 11 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_MCE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_SUE , 12 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_SUE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_AUE , 13 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_AUE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_UE , 14 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_UE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_RCD , 15 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_RCD ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_IAUE , 16 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_IAUE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_IUE , 17 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_IUE ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_IRCD , 18 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_IRCD ); +REG64_FLD( MCA_WDF_FIR_MAINLINE_IMPE , 19 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINLINE_IMPE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7 , 20 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_NCE , 28 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_NCE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_TCE , 29 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_TCE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_SCE , 30 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_SCE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_MCE , 31 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_MCE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_SUE , 32 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_SUE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_AUE , 33 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_AUE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_UE , 34 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_UE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_RCD , 35 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_RCD ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IAUE , 36 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_IAUE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IUE , 37 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_IUE ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IRCD , 38 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_IRCD ); +REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IMPE , 39 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_MAINTENANCE_IMPE ); +REG64_FLD( MCA_WDF_FIR_RESERVED_40 , 40 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_RESERVED_40 ); +REG64_FLD( MCA_WDF_FIR_SCOM_PARITY_CLASS_STATUS , 41 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_SCOM_PARITY_CLASS_STATUS ); +REG64_FLD( MCA_WDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE , 42 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE ); +REG64_FLD( MCA_WDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE , 43 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE ); +REG64_FLD( MCA_WDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR , 44 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR ); +REG64_FLD( MCA_WDF_FIR_WRITE_RMW_CE , 45 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WRITE_RMW_CE ); +REG64_FLD( MCA_WDF_FIR_WRITE_RMW_UE , 46 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WRITE_RMW_UE ); +REG64_FLD( MCA_WDF_FIR_WRITE_RMW_SUE , 47 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WRITE_RMW_SUE ); +REG64_FLD( MCA_WDF_FIR_WDF_OVERRUN_ERROR_0 , 48 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WDF_OVERRUN_ERROR_0 ); +REG64_FLD( MCA_WDF_FIR_WDF_OVERRUN_ERROR_1 , 49 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WDF_OVERRUN_ERROR_1 ); +REG64_FLD( MCA_WDF_FIR_WDF_SCOM_SEQUENCE_ERROR , 50 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WDF_SCOM_SEQUENCE_ERROR ); +REG64_FLD( MCA_WDF_FIR_WDF_STATE_MACHINE_ERROR , 51 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WDF_STATE_MACHINE_ERROR ); +REG64_FLD( MCA_WDF_FIR_WDF_MISC_REGISTER_PARITY_ERROR , 52 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR ); +REG64_FLD( MCA_WDF_FIR_WRT_SCOM_SEQUENCE_ERROR , 53 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WRT_SCOM_SEQUENCE_ERROR ); +REG64_FLD( MCA_WDF_FIR_WRT_MISC_REGISTER_PARITY_ERROR , 54 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR ); +REG64_FLD( MCA_WDF_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR , 55 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR ); +REG64_FLD( MCA_WDF_FIR_READ_BUFFER_OVERFLOW_ERROR , 56 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_READ_BUFFER_OVERFLOW_ERROR ); +REG64_FLD( MCA_WDF_FIR_WDF_ASYNC_INTERFACE_ERROR , 57 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_WDF_ASYNC_INTERFACE_ERROR ); +REG64_FLD( MCA_WDF_FIR_READ_ASYNC_INTERFACE_PARITY_ERROR , 58 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR ); +REG64_FLD( MCA_WDF_FIR_READ_ASYNC_INTERFACE_SEQUENCE_ERROR , 59 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR ); +REG64_FLD( MCA_WDF_FIR_RESERVED , 60 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_RESERVED ); +REG64_FLD( MCA_WDF_FIR_RESERVED_LEN , 2 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_RESERVED_LEN ); +REG64_FLD( MCA_WDF_FIR_INTERNAL_SCOM_ERROR , 62 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCA_WDF_FIR_INTERNAL_SCOM_ERROR_COPY , 63 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, + SH_FLD_INTERNAL_SCOM_ERROR_COPY ); + +REG64_FLD( MCA_FIR_MAINLINE_MPE_RANK_0_TO_7 , 0 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_MPE_RANK_0_TO_7 ); +REG64_FLD( MCA_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN ); +REG64_FLD( MCA_FIR_MAINLINE_NCE , 8 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_NCE ); +REG64_FLD( MCA_FIR_MAINLINE_TCE , 9 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_TCE ); +REG64_FLD( MCA_FIR_MAINLINE_SCE , 10 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_SCE ); +REG64_FLD( MCA_FIR_MAINLINE_MCE , 11 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_MCE ); +REG64_FLD( MCA_FIR_MAINLINE_SUE , 12 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_SUE ); +REG64_FLD( MCA_FIR_MAINLINE_AUE , 13 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_AUE ); +REG64_FLD( MCA_FIR_MAINLINE_UE , 14 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_UE ); +REG64_FLD( MCA_FIR_MAINLINE_RCD , 15 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_RCD ); +REG64_FLD( MCA_FIR_MAINLINE_IAUE , 16 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_IAUE ); +REG64_FLD( MCA_FIR_MAINLINE_IUE , 17 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_IUE ); +REG64_FLD( MCA_FIR_MAINLINE_IRCD , 18 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_IRCD ); +REG64_FLD( MCA_FIR_MAINLINE_IMPE , 19 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINLINE_IMPE ); +REG64_FLD( MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7 , 20 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 ); +REG64_FLD( MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN ); +REG64_FLD( MCA_FIR_MAINTENANCE_NCE , 28 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_NCE ); +REG64_FLD( MCA_FIR_MAINTENANCE_TCE , 29 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_TCE ); +REG64_FLD( MCA_FIR_MAINTENANCE_SCE , 30 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_SCE ); +REG64_FLD( MCA_FIR_MAINTENANCE_MCE , 31 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_MCE ); +REG64_FLD( MCA_FIR_MAINTENANCE_SUE , 32 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_SUE ); +REG64_FLD( MCA_FIR_MAINTENANCE_AUE , 33 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_AUE ); +REG64_FLD( MCA_FIR_MAINTENANCE_UE , 34 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_UE ); +REG64_FLD( MCA_FIR_MAINTENANCE_RCD , 35 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_RCD ); +REG64_FLD( MCA_FIR_MAINTENANCE_IAUE , 36 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_IAUE ); +REG64_FLD( MCA_FIR_MAINTENANCE_IUE , 37 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_IUE ); +REG64_FLD( MCA_FIR_MAINTENANCE_IRCD , 38 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_IRCD ); +REG64_FLD( MCA_FIR_MAINTENANCE_IMPE , 39 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MAINTENANCE_IMPE ); +REG64_FLD( MCA_FIR_RESERVED_40 , 40 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_40 ); +REG64_FLD( MCA_FIR_SCOM_PARITY_CLASS_STATUS , 41 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_PARITY_CLASS_STATUS ); +REG64_FLD( MCA_FIR_SCOM_PARITY_CLASS_RECOVERABLE , 42 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE ); +REG64_FLD( MCA_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE , 43 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE ); +REG64_FLD( MCA_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR , 44 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR ); +REG64_FLD( MCA_FIR_WRITE_RMW_CE , 45 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WRITE_RMW_CE ); +REG64_FLD( MCA_FIR_WRITE_RMW_UE , 46 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WRITE_RMW_UE ); +REG64_FLD( MCA_FIR_WRITE_RMW_SUE , 47 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WRITE_RMW_SUE ); +REG64_FLD( MCA_FIR_WDF_OVERRUN_ERROR_0 , 48 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WDF_OVERRUN_ERROR_0 ); +REG64_FLD( MCA_FIR_WDF_OVERRUN_ERROR_1 , 49 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WDF_OVERRUN_ERROR_1 ); +REG64_FLD( MCA_FIR_WDF_SCOM_SEQUENCE_ERROR , 50 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WDF_SCOM_SEQUENCE_ERROR ); +REG64_FLD( MCA_FIR_WDF_STATE_MACHINE_ERROR , 51 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WDF_STATE_MACHINE_ERROR ); +REG64_FLD( MCA_FIR_WDF_MISC_REGISTER_PARITY_ERROR , 52 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR ); +REG64_FLD( MCA_FIR_WRT_SCOM_SEQUENCE_ERROR , 53 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WRT_SCOM_SEQUENCE_ERROR ); +REG64_FLD( MCA_FIR_WRT_MISC_REGISTER_PARITY_ERROR , 54 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR ); +REG64_FLD( MCA_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR , 55 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR ); +REG64_FLD( MCA_FIR_READ_BUFFER_OVERFLOW_ERROR , 56 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_READ_BUFFER_OVERFLOW_ERROR ); +REG64_FLD( MCA_FIR_WDF_ASYNC_INTERFACE_ERROR , 57 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WDF_ASYNC_INTERFACE_ERROR ); +REG64_FLD( MCA_FIR_READ_ASYNC_INTERFACE_PARITY_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR ); +REG64_FLD( MCA_FIR_READ_ASYNC_INTERFACE_SEQUENCE_ERROR , 59 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR ); +REG64_FLD( MCA_FIR_RESERVED , 60 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED ); +REG64_FLD( MCA_FIR_RESERVED_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_LEN ); +REG64_FLD( MCA_FIR_INTERNAL_SCOM_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCA_FIR_INTERNAL_SCOM_ERROR_COPY , 63 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_COPY ); + +REG64_FLD( MCA_FWMS0_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_FWMS0_MARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_FWMS0_TYPE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_FWMS0_REGION , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_FWMS0_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_FWMS0_ADDRESS , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_FWMS0_ADDRESS_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_FWMS0_EXIT_1 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_WREITE_FWMS1_MARK , 0 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_WREITE_FWMS1_MARK_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_WREITE_FWMS1_TYPE , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_WREITE_FWMS1_REGION , 9 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_WREITE_FWMS1_REGION_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_WREITE_FWMS1_ADDRESS , 12 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_WREITE_FWMS1_ADDRESS_LEN , 11 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_WREITE_FWMS1_EXIT_1 , 23 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_FWMS2_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_FWMS2_MARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_FWMS2_TYPE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_FWMS2_REGION , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_FWMS2_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_FWMS2_ADDRESS , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_FWMS2_ADDRESS_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_FWMS2_EXIT_1 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_FWMS3_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_FWMS3_MARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_FWMS3_TYPE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_FWMS3_REGION , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_FWMS3_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_FWMS3_ADDRESS , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_FWMS3_ADDRESS_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_FWMS3_EXIT_1 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_FWMS4_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_FWMS4_MARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_FWMS4_TYPE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_FWMS4_REGION , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_FWMS4_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_FWMS4_ADDRESS , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_FWMS4_ADDRESS_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_FWMS4_EXIT_1 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_FWMS5_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_FWMS5_MARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_FWMS5_TYPE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_FWMS5_REGION , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_FWMS5_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_FWMS5_ADDRESS , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_FWMS5_ADDRESS_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_FWMS5_EXIT_1 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_FWMS6_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_FWMS6_MARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_FWMS6_TYPE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_FWMS6_REGION , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_FWMS6_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_FWMS6_ADDRESS , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_FWMS6_ADDRESS_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_FWMS6_EXIT_1 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_FWMS7_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK ); +REG64_FLD( MCA_FWMS7_MARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MARK_LEN ); +REG64_FLD( MCA_FWMS7_TYPE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TYPE ); +REG64_FLD( MCA_FWMS7_REGION , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION ); +REG64_FLD( MCA_FWMS7_REGION_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REGION_LEN ); +REG64_FLD( MCA_FWMS7_ADDRESS , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_FWMS7_ADDRESS_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_FWMS7_EXIT_1 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EXIT_1 ); + +REG64_FLD( MCA_HCA_ACCUM_REG_REG , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REG ); +REG64_FLD( MCA_HCA_ACCUM_REG_REG_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REG_LEN ); + +REG64_FLD( MCA_HWMS0_CHIPMARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_HWMS0_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_HWMS0_CONFIRMED , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_WDF_HWMS1_CHIPMARK , 0 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_WDF_HWMS1_CHIPMARK_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_WDF_HWMS1_CONFIRMED , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_HWMS2_CHIPMARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_HWMS2_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_HWMS2_CONFIRMED , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_HWMS3_CHIPMARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_HWMS3_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_HWMS3_CONFIRMED , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_HWMS4_CHIPMARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_HWMS4_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_HWMS4_CONFIRMED , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_HWMS5_CHIPMARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_HWMS5_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_HWMS5_CONFIRMED , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_HWMS6_CHIPMARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_HWMS6_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_HWMS6_CONFIRMED , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_HWMS7_CHIPMARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_HWMS7_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_HWMS7_CONFIRMED , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CONFIRMED ); + +REG64_FLD( MCA_MASK_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_FIR ); +REG64_FLD( MCA_MASK_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_FIR_LEN ); + +REG64_FLD( MCA_MBACALFIRQ_MBA_RECOVERABLE_ERROR , 0 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MBA_RECOVERABLE_ERROR ); +REG64_FLD( MCA_MBACALFIRQ_MBA_NONRECOVERABLE_ERROR , 1 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MBA_NONRECOVERABLE_ERROR ); +REG64_FLD( MCA_MBACALFIRQ_REFRESH_OVERRUN , 2 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_REFRESH_OVERRUN ); +REG64_FLD( MCA_MBACALFIRQ_WAT_ERROR , 3 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WAT_ERROR ); +REG64_FLD( MCA_MBACALFIRQ_RCD_PARITY_ERROR , 4 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_RCD_PARITY_ERROR ); +REG64_FLD( MCA_MBACALFIRQ_DDR_CAL_TIMEOUT_ERR , 5 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR_CAL_TIMEOUT_ERR ); +REG64_FLD( MCA_MBACALFIRQ_EMERGENCY_THROTTLE , 6 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_EMERGENCY_THROTTLE ); +REG64_FLD( MCA_MBACALFIRQ_DDR_CAL_RESET_TIMEOUT , 7 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR_CAL_RESET_TIMEOUT ); +REG64_FLD( MCA_MBACALFIRQ_DDR_MBA_EVENT_N , 8 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR_MBA_EVENT_N ); +REG64_FLD( MCA_MBACALFIRQ_WRQ_RRQ_HANG_ERR , 9 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WRQ_RRQ_HANG_ERR ); +REG64_FLD( MCA_MBACALFIRQ_SM_1HOT_ERR , 10 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_SM_1HOT_ERR ); +REG64_FLD( MCA_MBACALFIRQ_ASYNC_IF_ERROR , 11 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ASYNC_IF_ERROR ); +REG64_FLD( MCA_MBACALFIRQ_CMD_PARITY_ERROR , 12 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_CMD_PARITY_ERROR ); +REG64_FLD( MCA_MBACALFIRQ_RESERVED_13 , 13 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_13 ); +REG64_FLD( MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR , 14 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY , 15 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_COPY ); + +REG64_FLD( MCA_MBACALFIR_ACTION0_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FIR ); +REG64_FLD( MCA_MBACALFIR_ACTION0_FIR_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FIR_LEN ); + +REG64_FLD( MCA_MBACALFIR_ACTION1_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FIR ); +REG64_FLD( MCA_MBACALFIR_ACTION1_FIR_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FIR_LEN ); + +REG64_FLD( MCA_MBACALFIR_MASK_MBA_RECOVERABLE_ERROR , 0 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MBA_RECOVERABLE_ERROR ); +REG64_FLD( MCA_MBACALFIR_MASK_MBA_NONRECOVERABLE_ERROR , 1 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_MBA_NONRECOVERABLE_ERROR ); +REG64_FLD( MCA_MBACALFIR_MASK_REFRESH_OVERRUN , 2 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_REFRESH_OVERRUN ); +REG64_FLD( MCA_MBACALFIR_MASK_WAT_ERROR , 3 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WAT_ERROR ); +REG64_FLD( MCA_MBACALFIR_MASK_RCD_PARITY_ERROR , 4 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_RCD_PARITY_ERROR ); +REG64_FLD( MCA_MBACALFIR_MASK_DDR_CAL_TIMEOUT_ERR , 5 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR_CAL_TIMEOUT_ERR ); +REG64_FLD( MCA_MBACALFIR_MASK_EMERGENCY_THROTTLE , 6 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_EMERGENCY_THROTTLE ); +REG64_FLD( MCA_MBACALFIR_MASK_DDR_CAL_RESET_TIMEOUT , 7 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR_CAL_RESET_TIMEOUT ); +REG64_FLD( MCA_MBACALFIR_MASK_DDR_MBA_EVENT_N , 8 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR_MBA_EVENT_N ); +REG64_FLD( MCA_MBACALFIR_MASK_WRQ_RRQ_HANG_ERR , 9 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_WRQ_RRQ_HANG_ERR ); +REG64_FLD( MCA_MBACALFIR_MASK_SM_1HOT_ERR , 10 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_SM_1HOT_ERR ); +REG64_FLD( MCA_MBACALFIR_MASK_ASYNC_IF_ERROR , 11 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ASYNC_IF_ERROR ); +REG64_FLD( MCA_MBACALFIR_MASK_CMD_PARITY_ERROR , 12 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_CMD_PARITY_ERROR ); +REG64_FLD( MCA_MBACALFIR_MASK_RESERVED_13 , 13 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_13 ); +REG64_FLD( MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR , 14 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR_COPY , 15 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_COPY ); + +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_ENABLE ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN ); +REG64_FLD( MCA_MBAREF0Q_CFG_PER_BANK_REFRESH , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PER_BANK_REFRESH ); +REG64_FLD( MCA_MBAREF0Q_RESERVED_4 , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_4 ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_INTERVAL ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_INTERVAL_LEN ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_RESET_INTERVAL ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN ); +REG64_FLD( MCA_MBAREF0Q_CFG_TRFC , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRFC ); +REG64_FLD( MCA_MBAREF0Q_CFG_TRFC_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRFC_LEN ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFR_TSV_STACK , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFR_TSV_STACK ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFR_TSV_STACK_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFR_TSV_STACK_LEN ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFR_CHECK_INTERVAL ); +REG64_FLD( MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN ); +REG64_FLD( MCA_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF ); +REG64_FLD( MCA_MBAREF0Q_RESERVED_62_63 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63 ); +REG64_FLD( MCA_MBAREF0Q_RESERVED_62_63_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63_LEN ); + +REG64_FLD( MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_STATIC_IDLE_DLY ); +REG64_FLD( MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_STATIC_IDLE_DLY_LEN ); +REG64_FLD( MCA_MBAREFAQ_CFG_LP_SUB_CNT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_LP_SUB_CNT ); +REG64_FLD( MCA_MBAREFAQ_CFG_LP_SUB_CNT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_LP_SUB_CNT_LEN ); +REG64_FLD( MCA_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE ); +REG64_FLD( MCA_MBAREFAQ_RESERVED_7_9 , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_7_9 ); +REG64_FLD( MCA_MBAREFAQ_RESERVED_7_9_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_7_9_LEN ); +REG64_FLD( MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REF_BLOCK_STOP_DLY ); +REG64_FLD( MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN ); + +REG64_FLD( MCA_MBARPC0Q_RESERVED_0_1 , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1 ); +REG64_FLD( MCA_MBARPC0Q_RESERVED_0_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1_LEN ); +REG64_FLD( MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE ); +REG64_FLD( MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_MAX_DOMAINS ); +REG64_FLD( MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_MAX_DOMAINS_LEN ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AVAIL , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_AVAIL ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AVAIL_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_AVAIL_LEN ); +REG64_FLD( MCA_MBARPC0Q_CFG_PDN_PUP , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PDN_PUP ); +REG64_FLD( MCA_MBARPC0Q_CFG_PDN_PUP_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PDN_PUP_LEN ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_PDN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_PDN ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_PDN_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_PDN_LEN ); +REG64_FLD( MCA_MBARPC0Q_RESERVED_21 , 21 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_21 ); +REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE ); +REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME ); +REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE , 33 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME , 34 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN ); +REG64_FLD( MCA_MBARPC0Q_CFG_FORCE_SPARE_PUP , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_FORCE_SPARE_PUP ); +REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT , 43 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT ); +REG64_FLD( MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN , 44 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EMER_MIN_MAX_DOMAIN ); +REG64_FLD( MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN ); +REG64_FLD( MCA_MBARPC0Q_CFG_PUP_ALL_WRITES_PENDING , 47 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUP_ALL_WRITES_PENDING ); +REG64_FLD( MCA_MBARPC0Q_CFG_ALWAYS_WAIT_ACT_TIME , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME ); +REG64_FLD( MCA_MBARPC0Q_RESERVED_49_63 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_49_63 ); +REG64_FLD( MCA_MBARPC0Q_RESERVED_49_63_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_49_63_LEN ); + +REG64_FLD( MCA_MBASTR0Q_CFG_STR_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_STR_ENABLE ); +REG64_FLD( MCA_MBASTR0Q_CFG_DIS_CLK_IN_STR , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DIS_CLK_IN_STR ); +REG64_FLD( MCA_MBASTR0Q_CFG_ENTER_STR_TIME , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENTER_STR_TIME ); +REG64_FLD( MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENTER_STR_TIME_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_TCKESR , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TCKESR ); +REG64_FLD( MCA_MBASTR0Q_CFG_TCKESR_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TCKESR_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TCKSRE ); +REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRE_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TCKSRE_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRX , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TCKSRX ); +REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRX_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TCKSRX_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_TXSDLL , 27 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TXSDLL ); +REG64_FLD( MCA_MBASTR0Q_CFG_TXSDLL_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TXSDLL_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS , 38 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRFC_COUNTER_DIS ); +REG64_FLD( MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRFC_COUNTER_DIS_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL , 46 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SAFE_REFRESH_INTERVAL ); +REG64_FLD( MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL ); +REG64_FLD( MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN ); +REG64_FLD( MCA_MBASTR0Q_RESERVED_61_63 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63 ); +REG64_FLD( MCA_MBASTR0Q_RESERVED_61_63_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63_LEN ); + +REG64_FLD( MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBAUER0Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBAUER0Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBAUER1Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBAUER1Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBAUER2Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBAUER2Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBAUER3Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBAUER3Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_INTERVAL_TMR0_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0 , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TIME_BASE_TMR0 ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TIME_BASE_TMR0_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERVAL_COUNTER_TMR0 ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_ENABLE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL1_TYPE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_DDR_DONE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_ENABLE , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL2_TYPE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_DDR_DONE , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_ENABLE , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE , 25 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL3_TYPE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_DDR_DONE , 29 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_Z_SYNC ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB , 47 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_ENABLE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_SINGLE_RANK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR0_SINGLE_RANK ); +REG64_FLD( MCA_MBA_CAL0Q_INJECT_CAL0_PAR_ERROR , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_CAL0_PAR_ERROR ); +REG64_FLD( MCA_MBA_CAL0Q_INJECT_1HOT_SM_ERROR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_1HOT_SM_ERROR ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_SINGLE_PORT_MODE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_DBG_BUS_BIT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_BUS_BIT ); +REG64_FLD( MCA_MBA_CAL0Q_RESET_RECOVER , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESET_RECOVER ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_58_63 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_58_63 ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_58_63_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_58_63_LEN ); + +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1 , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TIME_BASE_TMR1 ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TIME_BASE_TMR1_LEN ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERVAL_COUNTER_TMR1 ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_ENABLE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL1_TYPE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_DDR_DONE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_ENABLE , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL2_TYPE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_DDR_DONE , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_ENABLE , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE , 25 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL3_TYPE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_DDR_DONE , 29 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_Z_SYNC ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_SINGLE_RANK , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR1_SINGLE_RANK ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_RANK_ENABLE ); +REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_RANK_ENABLE_LEN ); +REG64_FLD( MCA_MBA_CAL1Q_RESERVED_48_63 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_63 ); +REG64_FLD( MCA_MBA_CAL1Q_RESERVED_48_63_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_63_LEN ); + +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_INTERVAL_TMR2_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2 , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TIME_BASE_TMR2 ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TIME_BASE_TMR2_LEN ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERVAL_COUNTER_TMR2 ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_ENABLE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL1_TYPE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_DDR_DONE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_ENABLE , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL2_TYPE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_DDR_DONE , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_ENABLE , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE , 25 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL3_TYPE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_DDR_DONE , 29 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_Z_SYNC ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_SINGLE_RANK , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_SINGLE_RANK ); +REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_WAT_EVENT_ENABLE , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE ); +REG64_FLD( MCA_MBA_CAL2Q_RESERVED_41_63 , 41 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_41_63 ); +REG64_FLD( MCA_MBA_CAL2Q_RESERVED_41_63_LEN , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_41_63_LEN ); + +REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERNAL_ZQ_TB ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERNAL_ZQ_TB_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERNAL_ZQ_LENGTH ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EXTERNAL_ZQ_TB ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EXTERNAL_ZQ_LENGTH ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDCLK_SYSCLK_TB ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDCLK_SYSCLK_LENGTH ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DQS_ALIGNMENT_TB ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DQS_ALIGNMENT_LENGTH ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MPR_READEYE_TB ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MPR_READEYE_TB_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MPR_READEYE_LENGTH ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MPR_READEYE_LENGTH_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ALL_PERIODIC_TB ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ALL_PERIODIC_TB_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ALL_PERIODIC_LENGTH ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN ); +REG64_FLD( MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS ); +REG64_FLD( MCA_MBA_CAL3Q_RESERVED_61_63 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63 ); +REG64_FLD( MCA_MBA_CAL3Q_RESERVED_61_63_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63_LEN ); + +REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_START_DLY , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RODT_START_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_START_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RODT_START_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_END_DLY , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RODT_END_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_END_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RODT_END_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_START_DLY , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WODT_START_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_START_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WODT_START_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_END_DLY , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WODT_END_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_END_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WODT_END_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDONE_DLY , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRDONE_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDONE_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRDONE_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDATA_DLY , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRDATA_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDATA_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRDATA_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RDTAG_DLY , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDTAG_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDTAG_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RDTAG_MBX_CYCLE , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDTAG_MBX_CYCLE ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY , 43 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RODT_BC4_END_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RODT_BC4_END_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WODT_BC4_END_DLY ); +REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WODT_BC4_END_DLY_LEN ); +REG64_FLD( MCA_MBA_DSM0Q_RESERVED_55_63 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_55_63 ); +REG64_FLD( MCA_MBA_DSM0Q_RESERVED_55_63_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_55_63_LEN ); + +REG64_FLD( MCA_MBA_ERR_REPORTQ_WRQ_HANG , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRQ_HANG ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RRQ_HANG , 1 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RRQ_HANG ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_DSM_PE , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DSM_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_TMR_PE , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_TMR_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RRQ_PE , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RRQ_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_WRQ_PE , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRQ_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_PE , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FARB_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_PC_PE , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PC_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL0_PE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL0_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL1_PE , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL1_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL2_PE , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL2_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL3_PE , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL3_PE ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_DDR_IF_SM_1HOT , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DDR_IF_SM_1HOT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL_SM_1HOT , 13 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL_SM_1HOT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RANK_SM_1HOT , 14 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RANK_SM_1HOT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_PC_CAL_REFFSM_1HOT , 15 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PC_CAL_REFFSM_1HOT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_PC_CAL_PCFSM_1HOT , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PC_CAL_PCFSM_1HOT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_CAL_RECVFSM_1HOT , 17 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FARB_CAL_RECVFSM_1HOT ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_SIR_CERR , 18 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_SIR_CERR ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL0_INVALID_ACCESS , 19 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL0_INVALID_ACCESS ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL1_INVALID_ACCESS , 20 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL1_INVALID_ACCESS ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL2_INVALID_ACCESS , 21 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL2_INVALID_ACCESS ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL3_INVALID_ACCESS , 22 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CAL3_INVALID_ACCESS ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_DDR_INVALID_ACCESS , 23 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DDR_INVALID_ACCESS ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_CERR_24 , 24 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_CERR_24 ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_CERR_25 , 25 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_CERR_25 ); + +REG64_FLD( MCA_MBA_FARB0Q_CFG_MISR_BLOCK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MISR_BLOCK ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_MISR_BLOCK_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MISR_BLOCK_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MISR_FEEDBACK_ENABLE ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_2N_ADDR , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_2N_ADDR ); +REG64_FLD( MCA_MBA_FARB0Q_RESERVED_18_23 , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_23 ); +REG64_FLD( MCA_MBA_FARB0Q_RESERVED_18_23_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_23_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAX_READS_IN_A_ROW ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW , 31 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAX_WRITES_IN_A_ROW ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_AFTER_CMD , 38 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARITY_AFTER_CMD ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_WEN , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INJECT_PARITY_ERR_WEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5 , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 ); +REG64_FLD( MCA_MBA_FARB0Q_RESERVED_41_42 , 41 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_41_42 ); +REG64_FLD( MCA_MBA_FARB0Q_RESERVED_41_42_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_41_42_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME , 43 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARITY_DETECT_TIME ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARITY_DETECT_TIME_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RCD_PROTECTION_TIME ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RCD_PROTECTION_TIME_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DISABLE_RCD_RECOVERY ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALWAYS_ON , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_OE_ALWAYS_ON ); +REG64_FLD( MCA_MBA_FARB0Q_RESERVED_56 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56 ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_DISABLE_REFRESH_DURING_NOISE_WDW , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DISABLE_REFRESH_DURING_NOISE_WDW ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALL_CKE_POWERED_DOWN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_IGNORE_RCD_PARITY_ERR , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_IGNORE_RCD_PARITY_ERR ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_ENABLE_RCD_RW_RETRY , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENABLE_RCD_RW_RETRY ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_OPT_RD_SIZE ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_OPT_RD_SIZE_LEN ); + +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S0_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S0_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S1_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S1_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S2_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S2_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S3_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S3_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S4_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S4_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S5_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S5_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S6_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S6_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID , 21 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S7_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT0_S7_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S0_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S0_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID , 27 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S1_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S1_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S2_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S2_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID , 33 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S3_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S3_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S4_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S4_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S5_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S5_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S6_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S6_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID , 45 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S7_CID ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SLOT1_S7_CID_LEN ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_DIS_SMDR , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DIS_SMDR ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_RSV0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RSV0 ); +REG64_FLD( MCA_MBA_FARB1Q_CFG_RSV0_LEN , 14 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RSV0_LEN ); + +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK0_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK0_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK1_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK1_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK2_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK2_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK3_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK3_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK4_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK4_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK5_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK5_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK6_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK6_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK7_RD_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK7_RD_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK0_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK0_WR_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK1_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK1_WR_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK2_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK2_WR_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT , 44 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK3_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK3_WR_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK4_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK4_WR_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK5_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK5_WR_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK6_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK6_WR_ODT_LEN ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK7_WR_ODT ); +REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK7_WR_ODT_LEN ); + +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_N_PER_SLOT ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_N_PER_SLOT_LEN ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_N_PER_PORT ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_N_PER_PORT_LEN ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_M , 31 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_M ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_M_LEN , 14 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_M_LEN ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT , 45 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_RAS_WEIGHT ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_RAS_WEIGHT_LEN ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_CAS_WEIGHT ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_CAS_WEIGHT_LEN ); +REG64_FLD( MCA_MBA_FARB3Q_RESERVED_51 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_51 ); +REG64_FLD( MCA_MBA_FARB3Q_RESERVED_52 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_52 ); +REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NM_CHANGE_AFTER_SYNC ); +REG64_FLD( MCA_MBA_FARB3Q_RESERVED_54_63 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_54_63 ); +REG64_FLD( MCA_MBA_FARB3Q_RESERVED_54_63_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_54_63_LEN ); + +REG64_FLD( MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NOISE_WAIT_TIME ); +REG64_FLD( MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_NOISE_WAIT_TIME_LEN ); +REG64_FLD( MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRECHARGE_WAIT_TIME ); +REG64_FLD( MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN ); +REG64_FLD( MCA_MBA_FARB4Q_CFG_SIM_FAST_NOISE_WINDOW , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_SIM_FAST_NOISE_WINDOW ); +REG64_FLD( MCA_MBA_FARB4Q_RESERVED_23_26 , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_23_26 ); +REG64_FLD( MCA_MBA_FARB4Q_RESERVED_23_26_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_23_26_LEN ); +REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_N , 27 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EMERGENCY_N ); +REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_N_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EMERGENCY_N_LEN ); +REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_M , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EMERGENCY_M ); +REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_M_LEN , 14 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EMERGENCY_M_LEN ); +REG64_FLD( MCA_MBA_FARB4Q_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_63 ); +REG64_FLD( MCA_MBA_FARB4Q_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_63_LEN ); + +REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DDR_DPHY_NCLK ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DDR_DPHY_NCLK_LEN ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DDR_DPHY_PCLK ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DDR_DPHY_PCLK_LEN ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_RESETN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DDR_RESETN ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CCS_ADDR_MUX_SEL ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CCS_INST_RESET_ENABLE ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_GP_BIT_3_ENABLE , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_GP_BIT_3_ENABLE ); +REG64_FLD( MCA_MBA_FARB5Q_CFG_FORCE_MCLK_LOW_N , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_FORCE_MCLK_LOW_N ); +REG64_FLD( MCA_MBA_FARB5Q_RESERVED_56_63 , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_63 ); +REG64_FLD( MCA_MBA_FARB5Q_RESERVED_56_63_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_63_LEN ); + +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_0_1 , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1 ); +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_0_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1_LEN ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BW_SNAPSHOT ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BW_SNAPSHOT_LEN ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CKE_PUP_STATE ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CKE_PUP_STATE_LEN ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_STR_STATE , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_STR_STATE ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_DEPTH ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_DEPTH_LEN ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_DEPTH ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_DEPTH_LEN ); +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_28_31 , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_28_31_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28_31_LEN ); + +REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EMER_THROTTLE_IP ); +REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SAFE_REFRESH_MODE ); +REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP_CLR , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_EMER_THROTTLE_IP_CLR ); +REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE_CLR , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SAFE_REFRESH_MODE_CLR ); + +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_FIR_CCS_ERR_HOLD_OUT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_FIR_MCBFSM_ERR_HOLD_OUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCB_FIR_MCBFSM_ERR_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_CNTLQ_PE_HOLD_OUT , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCB_CNTLQ_PE_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_CCS_CNTLQ_PE_HOLD_OUT , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_CCS_CNTLQ_PE_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBCNTL_PE_HOLD_OUT , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBCNTL_PE_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBAGEN_PE_HOLD_OUT , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBAGEN_PE_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MAINT_CCS_PE_HOLD_OUT , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MAINT_CCS_PE_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBDGEN_PE_HOLD_OUT , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBDGEN_PE_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBERR_SCOM_PE_HOLD_OUT , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBERR_SCOM_PE_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_RESERVED_12_31 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_12_31 ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_RESERVED_12_31_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_12_31_LEN ); + +REG64_FLD( MCA_MBA_PMU0Q_READ_COUNT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_READ_COUNT ); +REG64_FLD( MCA_MBA_PMU0Q_READ_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_READ_COUNT_LEN ); +REG64_FLD( MCA_MBA_PMU0Q_WRITE_COUNT , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRITE_COUNT ); +REG64_FLD( MCA_MBA_PMU0Q_WRITE_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRITE_COUNT_LEN ); + +REG64_FLD( MCA_MBA_PMU1Q_ACTIVATE_COUNT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ACTIVATE_COUNT ); +REG64_FLD( MCA_MBA_PMU1Q_ACTIVATE_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ACTIVATE_COUNT_LEN ); +REG64_FLD( MCA_MBA_PMU1Q_PU_COUNTS , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PU_COUNTS ); +REG64_FLD( MCA_MBA_PMU1Q_PU_COUNTS_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PU_COUNTS_LEN ); + +REG64_FLD( MCA_MBA_PMU2Q_FRAME_COUNT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FRAME_COUNT ); +REG64_FLD( MCA_MBA_PMU2Q_FRAME_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FRAME_COUNT_LEN ); + +REG64_FLD( MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_LOW_IDLE_THRESHOLD ); +REG64_FLD( MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_LOW_IDLE_THRESHOLD_LEN ); +REG64_FLD( MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MED_IDLE_THRESHOLD ); +REG64_FLD( MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MED_IDLE_THRESHOLD_LEN ); +REG64_FLD( MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_HIGH_IDLE_THRESHOLD ); +REG64_FLD( MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_HIGH_IDLE_THRESHOLD_LEN ); + +REG64_FLD( MCA_MBA_PMU4Q_BASE_IDLE_COUNT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_BASE_IDLE_COUNT ); +REG64_FLD( MCA_MBA_PMU4Q_BASE_IDLE_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_BASE_IDLE_COUNT_LEN ); +REG64_FLD( MCA_MBA_PMU4Q_LOW_IDLE_COUNT , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LOW_IDLE_COUNT ); +REG64_FLD( MCA_MBA_PMU4Q_LOW_IDLE_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LOW_IDLE_COUNT_LEN ); + +REG64_FLD( MCA_MBA_PMU5Q_MED_IDLE_COUNT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_MED_IDLE_COUNT ); +REG64_FLD( MCA_MBA_PMU5Q_MED_IDLE_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_MED_IDLE_COUNT_LEN ); +REG64_FLD( MCA_MBA_PMU5Q_HIGH_IDLE_COUNT , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HIGH_IDLE_COUNT ); +REG64_FLD( MCA_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HIGH_IDLE_COUNT_LEN ); + +REG64_FLD( MCA_MBA_PMU6Q_TOTAL_GAP_COUNTS , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TOTAL_GAP_COUNTS ); +REG64_FLD( MCA_MBA_PMU6Q_TOTAL_GAP_COUNTS_LEN , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TOTAL_GAP_COUNTS_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_COUNT , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SPECIFIC_GAP_COUNT ); +REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_COUNT_LEN , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SPECIFIC_GAP_COUNT_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_GAP_LENGTH_ADDER , 36 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_GAP_LENGTH_ADDER ); +REG64_FLD( MCA_MBA_PMU6Q_GAP_LENGTH_ADDER_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_GAP_LENGTH_ADDER_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_CONDITION , 39 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SPECIFIC_GAP_CONDITION ); +REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_CONDITION_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SPECIFIC_GAP_CONDITION_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_CMD_TO_CMD_COUNT , 43 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMD_TO_CMD_COUNT ); +REG64_FLD( MCA_MBA_PMU6Q_CMD_TO_CMD_COUNT_LEN , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMD_TO_CMD_COUNT_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_COMMAND_PATTERN_TO_COUNT , 61 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_COMMAND_PATTERN_TO_COUNT ); +REG64_FLD( MCA_MBA_PMU6Q_COMMAND_PATTERN_TO_COUNT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_COMMAND_PATTERN_TO_COUNT_LEN ); + +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_SKIP_LIMIT ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_FIFO_MODE ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_SINGLE_THREAD_MODE , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_SINGLE_THREAD_MODE ); +REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_8_10 , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_10 ); +REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_8_10_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_10_LEN ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_DISABLE_RD_PG_MODE , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DISABLE_RD_PG_MODE ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_DISABLE_FAST_PATH , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DISABLE_FAST_PATH ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RD_IDLE_ALLOW_WR ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN ); +REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_37_56 , 37 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_37_56 ); +REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_37_56_LEN , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_37_56_LEN ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN ); +REG64_FLD( MCA_MBA_RRQ0Q_CFG_INJ_CANCEL_ACK_ERR , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_INJ_CANCEL_ACK_ERR ); +REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_60_63 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63 ); +REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_60_63_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63_LEN ); + +REG64_FLD( MCA_MBA_TMR0Q_RRDM_DLY , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRDM_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_RRDM_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRDM_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_RRSMSR_DLY , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRSMSR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_RRSMSR_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRSMSR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_RRSMDR_DLY , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRSMDR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_RRSMDR_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRSMDR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_RROP_DLY , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RROP_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_RROP_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RROP_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_WWDM_DLY , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWDM_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_WWDM_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWDM_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_WWSMSR_DLY , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWSMSR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_WWSMSR_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWSMSR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_WWSMDR_DLY , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWSMDR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_WWSMDR_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWSMDR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_WWOP_DLY , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWOP_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_WWOP_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WWOP_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_RWDM_DLY , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RWDM_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_RWDM_DLY_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RWDM_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_RWSMSR_DLY , 37 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RWSMSR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_RWSMSR_DLY_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RWSMSR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_RWSMDR_DLY , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RWSMDR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_RWSMDR_DLY_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RWSMDR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_WRDM_DLY , 47 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRDM_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_WRDM_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRDM_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_WRSMSR_DLY , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRSMSR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_WRSMSR_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRSMSR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_WRSMDR_DLY , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRSMDR_DLY ); +REG64_FLD( MCA_MBA_TMR0Q_WRSMDR_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRSMDR_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR0Q_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_63 ); + +REG64_FLD( MCA_MBA_TMR1Q_RRSBG_DLY , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRSBG_DLY ); +REG64_FLD( MCA_MBA_TMR1Q_RRSBG_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RRSBG_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_WRSBG_DLY , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRSBG_DLY ); +REG64_FLD( MCA_MBA_TMR1Q_WRSBG_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRSBG_DLY_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TFAW , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TFAW ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TFAW_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TFAW_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TRCD , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRCD ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TRCD_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRCD_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TRP , 21 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRP ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TRP_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRP_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TRAS , 26 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRAS ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_TRAS_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_TRAS_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_RESERVED_32_40 , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_40 ); +REG64_FLD( MCA_MBA_TMR1Q_RESERVED_32_40_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_40_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_WR2PRE , 41 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WR2PRE ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_WR2PRE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WR2PRE_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_RD2PRE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RD2PRE ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_RD2PRE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RD2PRE_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_TRRD , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRRD ); +REG64_FLD( MCA_MBA_TMR1Q_TRRD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRRD_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_TRRD_SBG , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRRD_SBG ); +REG64_FLD( MCA_MBA_TMR1Q_TRRD_SBG_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TRRD_SBG_LEN ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY ); +REG64_FLD( MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN ); + +REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BANK_BUSY_FSM_DIS ); +REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS_LEN , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN ); +REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS ); +REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN ); +REG64_FLD( MCA_MBA_TMR2Q_CFG_AUTOPC_THRESHOLD , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_AUTOPC_THRESHOLD ); +REG64_FLD( MCA_MBA_TMR2Q_CFG_AUTOPC_THRESHOLD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_AUTOPC_THRESHOLD_LEN ); +REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63 , 35 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_63 ); +REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63_LEN , 29 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_63_LEN ); + +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_HW_MARK ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_HW_MARK_LEN ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_FIFO_MODE ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DISABLE_WR_PG_MODE ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_ENTRY0_HP_DLY ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_FLUSH_WR_RANK ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR , 21 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK , 33 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_LW_MARK ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_LW_MARK_LEN ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT , 38 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_SKIP_LIMIT ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_SINGLE_THREAD_MODE , 44 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_SINGLE_THREAD_MODE ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD , 45 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RQ_HANG_THRESHOLD ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN ); +REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_53 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_53 ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_FRC_ST_RD_HIT_WR , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_FRC_ST_RD_HIT_WR ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING ); +REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN ); +REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_57_63 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_57_63 ); +REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_57_63_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_57_63_LEN ); + +REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_CE_INJ , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ATOMIC_ALT_CE_INJ ); +REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ ); +REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_UE_INJ , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ATOMIC_ALT_UE_INJ ); +REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_SUE_INJ , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ATOMIC_ALT_SUE_INJ ); +REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ATOMIC_ALT_INJ_SYM_SEL ); +REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN ); +REG64_FLD( MCBIST_MBECTLQ_RESERVE_11 , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVE_11 ); +REG64_FLD( MCBIST_MBECTLQ_SCOM_CMD_REG_INJ_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_CMD_REG_INJ_MODE ); +REG64_FLD( MCBIST_MBECTLQ_SCOM_CMD_REG_INJ , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_CMD_REG_INJ ); +REG64_FLD( MCBIST_MBECTLQ_MCBIST_FSM_INJ_MODE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_FSM_INJ_MODE ); +REG64_FLD( MCBIST_MBECTLQ_MCBIST_FSM_INJ_REG , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_FSM_INJ_REG ); +REG64_FLD( MCBIST_MBECTLQ_CCS_FSM_INJ_MODE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_FSM_INJ_MODE ); +REG64_FLD( MCBIST_MBECTLQ_CCS_FSM_INJ_REG , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CCS_FSM_INJ_REG ); +REG64_FLD( MCBIST_MBECTLQ_RESERVED_18_31 , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( MCBIST_MBECTLQ_RESERVED_18_31_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_31_LEN ); + +REG64_FLD( MCA_MBMDI_MDI_0 , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MDI_0 ); +REG64_FLD( MCA_MBMDI_SUE_0 , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SUE_0 ); +REG64_FLD( MCA_MBMDI_MDI_1 , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MDI_1 ); +REG64_FLD( MCA_MBMDI_SUE_1 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SUE_1 ); + +REG64_FLD( MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE ); +REG64_FLD( MCBIST_MBMPER0Q_RESERVED_39 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39 ); + +REG64_FLD( MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE ); +REG64_FLD( MCBIST_MBMPER1Q_RESERVED_39 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39 ); + +REG64_FLD( MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE ); +REG64_FLD( MCBIST_MBMPER2Q_RESERVED_39 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39 ); + +REG64_FLD( MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE ); +REG64_FLD( MCBIST_MBMPER3Q_RESERVED_39 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39 ); + +REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE ); +REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE ); + +REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE ); +REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_IS_TCE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE ); + +REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE ); +REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_IS_TCE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE ); + +REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ON_RCE , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE ); +REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_IS_TCE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE ); + +REG64_FLD( MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBRCER0Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBRCER0Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBRCER1Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBRCER1Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBRCER2Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBRCER2Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBRCER3Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBRCER3Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERMITTENT_CE_COUNT ); +REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERMITTENT_CE_COUNT_LEN ); +REG64_FLD( MCBIST_MBSEC0Q_SOFT_CE_COUNT , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SOFT_CE_COUNT ); +REG64_FLD( MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SOFT_CE_COUNT_LEN ); +REG64_FLD( MCBIST_MBSEC0Q_HARD_CE_COUNT , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_HARD_CE_COUNT ); +REG64_FLD( MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_HARD_CE_COUNT_LEN ); +REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERMITTENT_MCE_COUNT ); +REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERMITTENT_MCE_COUNT_LEN ); +REG64_FLD( MCBIST_MBSEC0Q_SOFT_MCE_COUNT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SOFT_MCE_COUNT ); +REG64_FLD( MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SOFT_MCE_COUNT_LEN ); + +REG64_FLD( MCBIST_MBSEC1Q_HARD_MCE_COUNT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_HARD_MCE_COUNT ); +REG64_FLD( MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_HARD_MCE_COUNT_LEN ); +REG64_FLD( MCBIST_MBSEC1Q_ICE_COUNT , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ICE_COUNT ); +REG64_FLD( MCBIST_MBSEC1Q_ICE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ICE_COUNT_LEN ); +REG64_FLD( MCBIST_MBSEC1Q_UE_COUNT , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_UE_COUNT ); +REG64_FLD( MCBIST_MBSEC1Q_UE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_UE_COUNT_LEN ); +REG64_FLD( MCBIST_MBSEC1Q_AUE , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_AUE ); +REG64_FLD( MCBIST_MBSEC1Q_AUE_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_AUE_LEN ); +REG64_FLD( MCBIST_MBSEC1Q_RCE_COUNT , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RCE_COUNT ); +REG64_FLD( MCBIST_MBSEC1Q_RCE_COUNT_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RCE_COUNT_LEN ); + +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN ); + +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD ); +REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN ); + +REG64_FLD( MCBIST_MBSMODESQ_CFG_DDR4E_BLIND_STEER_MODE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DDR4E_BLIND_STEER_MODE ); +REG64_FLD( MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS ); +REG64_FLD( MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN ); +REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_63 , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVE_5_63 ); +REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_63_LEN , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVE_5_63_LEN ); + +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL0_COUNT ); +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL0_COUNT_LEN ); +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL1_COUNT ); +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL1_COUNT_LEN ); +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL2_COUNT ); +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL2_COUNT_LEN ); +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL3_COUNT ); +REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCE_SYMBOL3_COUNT_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_00 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_01 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_02 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_03 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_04 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_05 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_06 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_07 ); +REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_08 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_09 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_10 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_11 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_12 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_13 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_14 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_15 ); +REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_16 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_17 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_18 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_19 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_20 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_21 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_22 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_23 ); +REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_24 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_25 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_26 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_27 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_28 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_29 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_30 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_31 ); +REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_32 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_33 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_34 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_35 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_36 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_37 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_38 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_39 ); +REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_40 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_41 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_42 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_43 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_44 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_45 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_46 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_47 ); +REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_48 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_49 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_50 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_51 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_52 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_53 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_54 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_55 ); +REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_56 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_57 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_58 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_59 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_60 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_61 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_62 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_63 ); +REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN ); + +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_64 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_65 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_66 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_67 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_68 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_69 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_70 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_71 ); +REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN ); + +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_NCE_INT ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_NCE_SOFT ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_NCE_HARD ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_RCE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_RCE_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_ICE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_ICE_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_MCE_INT ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_MCE_SOFT ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_MCE_HARD ); +REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_SCE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MCE , 33 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_MCE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_MPE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_UE , 35 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_UE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_SUE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_AUE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_RCD ); +REG64_FLD( MCBIST_MBSTRQ_RESERVE_39_52 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVE_39_52 ); +REG64_FLD( MCBIST_MBSTRQ_RESERVE_39_52_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVE_39_52_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_SYMBOL_COUNTER_MODE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN ); +REG64_FLD( MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR , 58 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_MCB_ERROR ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_MCB_LOG_FULL ); +REG64_FLD( MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAINT_RCE_WITH_CE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE ); +REG64_FLD( MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE , 63 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE ); + +REG64_FLD( MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBUER0Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBUER0Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBUER1Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBUER1Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBUER2Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBUER2Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP ); +REG64_FLD( MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MBUER3Q_RESERVED_38_39 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39 ); +REG64_FLD( MCBIST_MBUER3Q_RESERVED_38_39_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_39_LEN ); + +REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_CLEAN , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_CLEAN ); +REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_READ_DATA_FROM_AMOC , 1 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_READ_DATA_FROM_AMOC ); +REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_READ_DATA_FROM_AMOC_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN ); +REG64_FLD( MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WRTO_AMO_COLLISION_RULES ); +REG64_FLD( MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN , 25 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WRTO_AMO_COLLISION_RULES_LEN ); +REG64_FLD( MCS_PORT02_MCAMOC_AMO_DRAM_SIZE_128B , 29 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_AMO_DRAM_SIZE_128B ); +REG64_FLD( MCS_PORT02_MCAMOC_RESERVED1 , 30 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED1 ); +REG64_FLD( MCS_PORT02_MCAMOC_RESERVED1_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_CLEAN , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_CLEAN ); +REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_READ_DATA_FROM_AMOC , 1 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_READ_DATA_FROM_AMOC ); +REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_READ_DATA_FROM_AMOC_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN ); +REG64_FLD( MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WRTO_AMO_COLLISION_RULES ); +REG64_FLD( MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN , 25 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WRTO_AMO_COLLISION_RULES_LEN ); +REG64_FLD( MCS_PORT13_MCAMOC_AMO_DRAM_SIZE_128B , 29 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_AMO_DRAM_SIZE_128B ); +REG64_FLD( MCS_PORT13_MCAMOC_RESERVED1 , 30 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED1 ); +REG64_FLD( MCS_PORT13_MCAMOC_RESERVED1_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( MCBIST_MCBACQ_CFG_ADDRESS_COUNTER , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_ADDRESS_COUNTER ); +REG64_FLD( MCBIST_MCBACQ_CFG_ADDRESS_COUNTER_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_ADDRESS_COUNTER_LEN ); + +REG64_FLD( MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_WIDTH ); +REG64_FLD( MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_WIDTH_LEN ); +REG64_FLD( MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_ADDR_COUNTER_MODE ); +REG64_FLD( MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_ADDR_COUNTER_MODE_LEN ); +REG64_FLD( MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAINT_ADDR_MODE_EN ); +REG64_FLD( MCBIST_MCBAGRAQ_CFG_MAINT_BROADCAST_MODE_EN , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAINT_BROADCAST_MODE_EN ); +REG64_FLD( MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MAINT_DETECT_SRANK_BOUNDARIES ); +REG64_FLD( MCBIST_MCBAGRAQ_RESERVED_13_31 , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_13_31 ); +REG64_FLD( MCBIST_MCBAGRAQ_RESERVED_13_31_LEN , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_13_31_LEN ); + +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_DIMM_SELECT ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_DIMM_SELECT_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0 , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_MRANK0 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_MRANK0_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_MRANK1 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_MRANK1_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_18_23 , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_23 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_18_23_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_23_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_SRANK0 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_SRANK0_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1 , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_SRANK1 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_SRANK1_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_SRANK2 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_SRANK2_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2 , 42 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK2 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK2_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK1 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK1_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0 , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK0 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK0_LEN ); +REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_60_63 , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63 ); +REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_60_63_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63_LEN ); + +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK_GROUP1 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK_GROUP1_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0 , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK_GROUP0 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_BANK_GROUP0_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW17 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW17_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16 , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW16 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW16_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW15 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW15_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14 , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW14 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW14_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW13 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW13_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 , 42 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW12 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW12_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW11 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW11_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10 , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW10 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW10_LEN ); +REG64_FLD( MCBIST_MCBAMR1A0Q_RESERVED_60_63 , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63 ); +REG64_FLD( MCBIST_MCBAMR1A0Q_RESERVED_60_63_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63_LEN ); + +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW9 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW9_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8 , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW8 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW8_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW7 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW7_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6 , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW6 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW6_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW5 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW5_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4 , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW4 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW4_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW3 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW3_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2 , 42 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW2 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW2_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW1 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW1_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0 , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW0 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_ROW0_LEN ); +REG64_FLD( MCBIST_MCBAMR2A0Q_RESERVED_60_63 , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63 ); +REG64_FLD( MCBIST_MCBAMR2A0Q_RESERVED_60_63_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63_LEN ); + +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL9 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL9_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8 , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL8 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL8_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL7 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL7_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6 , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL6 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL6_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL5 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL5_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4 , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL4 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL4_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL3 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL3_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2 , 42 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL2 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_AMAP_COL2_LEN ); +REG64_FLD( MCBIST_MCBAMR3A0Q_RESERVED_48_63 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_63 ); +REG64_FLD( MCBIST_MCBAMR3A0Q_RESERVED_48_63_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_63_LEN ); + +REG64_FLD( MCBIST_MCBCFGQ_BROADCAST_SYNC_EN , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_BROADCAST_SYNC_EN ); +REG64_FLD( MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_BROADCAST_SYNC_WAIT ); +REG64_FLD( MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT_LEN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_BROADCAST_SYNC_WAIT_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD_TIMEOUT_MODE ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD_TIMEOUT_MODE_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_RESET_KEEPER , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESET_KEEPER ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_12_34 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_34 ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_12_34_LEN , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_34_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK , 35 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RESET_CNTS_START_OF_RANK ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_LOG_COUNTS_IN_TRACE ); +REG64_FLD( MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SKIP_INVALID_ADDR_DIMM_DIS ); +REG64_FLD( MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_ONLY_SUBTEST_EN ); +REG64_FLD( MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL ); +REG64_FLD( MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN ); +REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME , 42 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_REF_WAIT_TIME ); +REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_MCB_LEN64 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MCB_LEN64 ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_ERROR_MODE ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST ); +REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR ); +REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_62 , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62 ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_63 , 63 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_63 ); + +REG64_FLD( MCA_MCBCM_MCBIST_HALF_COMPARE_MASK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_HALF_COMPARE_MASK ); +REG64_FLD( MCA_MCBCM_MCBIST_HALF_COMPARE_MASK_LEN , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN ); +REG64_FLD( MCA_MCBCM_MCBIST_MASK_COVERAGE_SELECTOR , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR ); +REG64_FLD( MCA_MCBCM_MCBIST_TRAP_NONSTOP , 41 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_TRAP_NONSTOP ); +REG64_FLD( MCA_MCBCM_MCBIST_TRAP_CE_ENABLE , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_TRAP_CE_ENABLE ); +REG64_FLD( MCA_MCBCM_MCBIST_TRAP_MPE_ENABLE , 43 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_TRAP_MPE_ENABLE ); +REG64_FLD( MCA_MCBCM_MCBIST_TRAP_UE_ENABLE , 44 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_TRAP_UE_ENABLE ); + +REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_ROT ); +REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_ROT_LEN ); +REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_ROT_SEED ); +REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_ROT_SEED_LEN ); +REG64_FLD( MCBIST_MCBDRCRQ_CFG_INVERT_DATA , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_INVERT_DATA ); +REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_SEED_MODE ); +REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_SEED_MODE_LEN ); +REG64_FLD( MCBIST_MCBDRCRQ_RESERVED_23_63 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_23_63 ); +REG64_FLD( MCBIST_MCBDRCRQ_RESERVED_23_63_LEN , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_23_63_LEN ); + +REG64_FLD( MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_ROT_SEED ); +REG64_FLD( MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DATA_ROT_SEED_LEN ); + +REG64_FLD( MCBIST_MCBEA0Q_CFG_END_ADDR_0 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_0 ); +REG64_FLD( MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_0_LEN ); + +REG64_FLD( MCBIST_MCBEA1Q_CFG_END_ADDR_1 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_1 ); +REG64_FLD( MCBIST_MCBEA1Q_CFG_END_ADDR_1_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_1_LEN ); + +REG64_FLD( MCBIST_MCBEA2Q_CFG_END_ADDR_2 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_2 ); +REG64_FLD( MCBIST_MCBEA2Q_CFG_END_ADDR_2_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_2_LEN ); + +REG64_FLD( MCBIST_MCBEA3Q_CFG_END_ADDR_3 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_3 ); +REG64_FLD( MCBIST_MCBEA3Q_CFG_END_ADDR_3_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_END_ADDR_3_LEN ); + +REG64_FLD( MCBIST_MCBFD0Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD0Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFD1Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD1Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFD2Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD2Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFD3Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD3Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFD4Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD4Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFD5Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD5Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFD6Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD6Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFD7Q_CFG_FIXED_SEED , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED ); +REG64_FLD( MCBIST_MCBFD7Q_CFG_FIXED_SEED_LEN , 64 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED_LEN ); + +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED1 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED1 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED1_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED1_LEN ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED2 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED2 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED2_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED2_LEN ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED3 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED3 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED3_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED3_LEN ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED4 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED4 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED4_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED4_LEN ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED5 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED5 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED5_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED5_LEN ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED6 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED6 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED6_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED6_LEN ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED7 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED7 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED7_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED7_LEN ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED8 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED8 ); +REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_FIXED_SEED8_LEN ); + +REG64_FLD( MCBIST_MCBISTFIRACT0_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INVALID_MAINT_ADDRESS ); +REG64_FLD( MCBIST_MCBISTFIRACT0_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_COMMAND_ADDRESS_TIMEOUT ); +REG64_FLD( MCBIST_MCBISTFIRACT0_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERNAL_FSM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); +REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_DATA_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRACT0_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_HARD_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT0_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SOFT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT0_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT0_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT0_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ICE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_PROGRAM_COMPLETE ); +REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CCS_SUBTEST_DONE ); +REG64_FLD( MCBIST_MCBISTFIRACT0_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_WAT_DEBUG_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT0_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_RECOVERABLE_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRACT0_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FATAL_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRACT0_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_15 ); +REG64_FLD( MCBIST_MCBISTFIRACT0_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16 ); +REG64_FLD( MCBIST_MCBISTFIRACT0_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_17 ); +REG64_FLD( MCBIST_MCBISTFIRACT0_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRACT0_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( MCBIST_MCBISTFIRACT1_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INVALID_MAINT_ADDRESS ); +REG64_FLD( MCBIST_MCBISTFIRACT1_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_COMMAND_ADDRESS_TIMEOUT ); +REG64_FLD( MCBIST_MCBISTFIRACT1_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERNAL_FSM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); +REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_DATA_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRACT1_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_HARD_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT1_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SOFT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT1_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT1_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT1_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_ICE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_PROGRAM_COMPLETE ); +REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CCS_SUBTEST_DONE ); +REG64_FLD( MCBIST_MCBISTFIRACT1_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_WAT_DEBUG_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRACT1_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_RECOVERABLE_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRACT1_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FATAL_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRACT1_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_15 ); +REG64_FLD( MCBIST_MCBISTFIRACT1_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16 ); +REG64_FLD( MCBIST_MCBISTFIRACT1_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_17 ); +REG64_FLD( MCBIST_MCBISTFIRACT1_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRACT1_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( MCBIST_MCBISTFIRMASK_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INVALID_MAINT_ADDRESS ); +REG64_FLD( MCBIST_MCBISTFIRMASK_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_COMMAND_ADDRESS_TIMEOUT ); +REG64_FLD( MCBIST_MCBISTFIRMASK_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_FSM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); +REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_DATA_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRMASK_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_HARD_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRMASK_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_SOFT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRMASK_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRMASK_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRMASK_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_ICE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_PROGRAM_COMPLETE ); +REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_CCS_SUBTEST_DONE ); +REG64_FLD( MCBIST_MCBISTFIRMASK_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_WAT_DEBUG_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRMASK_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_RECOVERABLE_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRMASK_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_FATAL_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRMASK_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_15 ); +REG64_FLD( MCBIST_MCBISTFIRMASK_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_16 ); +REG64_FLD( MCBIST_MCBISTFIRMASK_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_17 ); +REG64_FLD( MCBIST_MCBISTFIRMASK_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRMASK_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INVALID_MAINT_ADDRESS ); +REG64_FLD( MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_COMMAND_ADDRESS_TIMEOUT ); +REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_FSM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); +REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_DATA_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRQ_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_HARD_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRQ_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_SOFT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRQ_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRQ_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRQ_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_ICE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_PROGRAM_COMPLETE ); +REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_MCBIST_CCS_SUBTEST_DONE ); +REG64_FLD( MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_WAT_DEBUG_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_RECOVERABLE_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_FATAL_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_15 ); +REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_16 ); +REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED_17 ); +REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_INVALID_MAINT_ADDRESS ); +REG64_FLD( MCBIST_MCBISTFIRWOF_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_COMMAND_ADDRESS_TIMEOUT ); +REG64_FLD( MCBIST_MCBISTFIRWOF_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_INTERNAL_FSM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); +REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_DATA_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRWOF_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_HARD_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRWOF_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_SOFT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRWOF_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_INT_NCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRWOF_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RCE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRWOF_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_ICE_ETE_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_PROGRAM_COMPLETE ); +REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_CCS_SUBTEST_DONE ); +REG64_FLD( MCBIST_MCBISTFIRWOF_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_WAT_DEBUG_ATTN ); +REG64_FLD( MCBIST_MCBISTFIRWOF_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_SCOM_RECOVERABLE_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRWOF_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_SCOM_FATAL_REG_PE ); +REG64_FLD( MCBIST_MCBISTFIRWOF_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_15 ); +REG64_FLD( MCBIST_MCBISTFIRWOF_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_16 ); +REG64_FLD( MCBIST_MCBISTFIRWOF_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_17 ); +REG64_FLD( MCBIST_MCBISTFIRWOF_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCBIST_MCBISTFIRWOF_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_LFSR_MASK_A0 ); +REG64_FLD( MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_LFSR_MASK_A0_LEN ); +REG64_FLD( MCBIST_MCBLFSRA0Q_RESERVED_38_63 , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_63 ); +REG64_FLD( MCBIST_MCBLFSRA0Q_RESERVED_38_63_LEN , 26 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_38_63_LEN ); + +REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CURRENT_ADDR_TRAP ); +REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN ); +REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_PORT_DIMM_TRAP , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP ); +REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_PORT_DIMM_TRAP_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP_LEN ); + +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_DONE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_DONE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_DONE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_DONE ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_DONE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_DONE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_DONE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_DONE ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_DONE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_DONE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_DONE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_DONE ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_DONE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_DONE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_DONE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_DONE ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_DONE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_DONE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_DONE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_DONE ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_DONE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_DONE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_DONE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_DONE ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_DONE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_DONE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_DONE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_DONE ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_REV_MODE , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_RAND_MODE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ECC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DONE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_DONE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_REV_MODE , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_RAND_MODE , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ECC_MODE , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DONE , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_DONE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL , 30 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_REV_MODE , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_RAND_MODE , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ECC_MODE , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DONE , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_DONE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_OP_TYPE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD , 54 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_REV_MODE , 55 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_RAND_MODE , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE , 57 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_DATA_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ECC_MODE , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_ECC_MODE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DONE , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_DONE ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL ); +REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN ); + +REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_CMD_GAP ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_CMD_GAP_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_GAP_TIMEBASE ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER , 25 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_MIN_GAP_TIMEBASE_BLIND_STEER ); +REG64_FLD( MCBIST_MCBPARMQ_RESERVED_26_49 , 26 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_26_49 ); +REG64_FLD( MCBIST_MCBPARMQ_RESERVED_26_49_LEN , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_26_49_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDCMD_WGT , 50 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANDCMD_WGT ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANDCMD_WGT_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_59 , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_53_59 ); +REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_59_LEN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_53_59_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_EN_RANDCMD_GAP ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDGAP_WGT , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANDGAP_WGT ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANDGAP_WGT_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_BC4_EN , 63 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_BC4_EN ); + +REG64_FLD( MCBIST_MCBRCRQ_RESERVED_0_31 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_31 ); +REG64_FLD( MCBIST_MCBRCRQ_RESERVED_0_31_LEN , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_31_LEN ); +REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_MCBALL , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RUNTIME_MCBALL ); +REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST , 33 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RUNTIME_SUBTEST ); +REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RUNTIME_SUBTEST_LEN ); +REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_OVERHEAD , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RUNTIME_OVERHEAD ); +REG64_FLD( MCBIST_MCBRCRQ_RESERVED_39 , 39 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_39 ); + +REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_SEED0 ); +REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_SEED0_LEN ); +REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_SEED1 ); +REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_SEED1_LEN ); + +REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_SEED2 ); +REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_SEED2_LEN ); +REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_DATA_MAPPING ); +REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN ); + +REG64_FLD( MCBIST_MCBSA0Q_CFG_START_ADDR_0 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_0 ); +REG64_FLD( MCBIST_MCBSA0Q_CFG_START_ADDR_0_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_0_LEN ); + +REG64_FLD( MCBIST_MCBSA1Q_CFG_START_ADDR_1 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_1 ); +REG64_FLD( MCBIST_MCBSA1Q_CFG_START_ADDR_1_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_1_LEN ); + +REG64_FLD( MCBIST_MCBSA2Q_CFG_START_ADDR_2 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_2 ); +REG64_FLD( MCBIST_MCBSA2Q_CFG_START_ADDR_2_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_2_LEN ); + +REG64_FLD( MCBIST_MCBSA3Q_CFG_START_ADDR_3 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_3 ); +REG64_FLD( MCBIST_MCBSA3Q_CFG_START_ADDR_3_LEN , 38 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_START_ADDR_3_LEN ); + +REG64_FLD( MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR ); +REG64_FLD( MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN ); +REG64_FLD( MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR ); +REG64_FLD( MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR_LEN ); +REG64_FLD( MCBIST_MCBSTATQ_RESERVED_9_15 , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_9_15 ); +REG64_FLD( MCBIST_MCBSTATQ_RESERVED_9_15_LEN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_9_15_LEN ); + +REG64_FLD( MCS_PORT02_MCBUSYQ_ENABLE_BUSY_COUNTERS , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_BUSY_COUNTERS ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT , 1 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_WINDOW_SELECT ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0 , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD0 ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1 , 14 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD1 ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 , 24 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD2 ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD3 , 34 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD3 ); +REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD3_LEN , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD3_LEN ); + +REG64_FLD( MCS_PORT13_MCBUSYQ_ENABLE_BUSY_COUNTERS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_BUSY_COUNTERS ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT , 1 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_WINDOW_SELECT ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0 , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD0 ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN , 10 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1 , 14 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD1 ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN , 10 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 , 24 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD2 ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN , 10 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD3 , 34 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD3 ); +REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD3_LEN , 10 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BUSY_COUNTER_THRESHOLD3_LEN ); + +REG64_FLD( MCBIST_MCB_CNTLQ_START , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_START ); +REG64_FLD( MCBIST_MCB_CNTLQ_STOP , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_STOP ); +REG64_FLD( MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBCNTL_PORT_SEL ); +REG64_FLD( MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBCNTL_PORT_SEL_LEN ); +REG64_FLD( MCBIST_MCB_CNTLQ_RESET_TRAP_CNFG , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESET_TRAP_CNFG ); +REG64_FLD( MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESET_ERROR_LOGS ); +REG64_FLD( MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESUME_FROM_PAUSE ); + +REG64_FLD( MCBIST_MCB_CNTLSTATQ_IP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_IP ); +REG64_FLD( MCBIST_MCB_CNTLSTATQ_DONE , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_DONE ); +REG64_FLD( MCBIST_MCB_CNTLSTATQ_FAIL , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FAIL ); + +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE0_SEL , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE0_SEL ); +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE0_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE0_SEL_LEN ); +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE1_SEL , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE1_SEL ); +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE1_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE1_SEL_LEN ); +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE2_SEL , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE2_SEL ); +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE2_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE2_SEL_LEN ); +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE3_SEL , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE3_SEL ); +REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE3_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BYTE3_SEL_LEN ); +REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHA , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHA ); +REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHA_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHA_LEN ); +REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHB , 16 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHB ); +REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHB_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHB_LEN ); +REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHC , 24 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHC ); +REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHC_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHC_LEN ); + +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE0_SEL , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE0_SEL ); +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE0_SEL_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE0_SEL_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE1_SEL , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE1_SEL ); +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE1_SEL_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE1_SEL_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE2_SEL , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE2_SEL ); +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE2_SEL_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE2_SEL_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE3_SEL , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE3_SEL ); +REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE3_SEL_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BYTE3_SEL_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHA , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHA ); +REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHA_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHA_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHB , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHB ); +REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHB_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHB_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHC , 24 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHC ); +REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHC_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LAT_THRESHC_LEN ); + +REG64_FLD( MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_SELECTS ); +REG64_FLD( MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS_LEN , 64 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_SELECTS_LEN ); + +REG64_FLD( MCS_PORT13_MCEBUSEN1_MCEBUSEN0_EVENT_BUS_SELECTS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_MCEBUSEN0_EVENT_BUS_SELECTS ); +REG64_FLD( MCS_PORT13_MCEBUSEN1_MCEBUSEN0_EVENT_BUS_SELECTS_LEN , 64 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_MCEBUSEN0_EVENT_BUS_SELECTS_LEN ); + +REG64_FLD( MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_SELECTS ); +REG64_FLD( MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS_LEN , 64 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_SELECTS_LEN ); + +REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_EN ); +REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN_LEN , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_EN_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_ENABLE , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_ENABLE ); + +REG64_FLD( MCS_PORT02_MCEPSQ_JITTER_EPSILON , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_JITTER_EPSILON ); +REG64_FLD( MCS_PORT02_MCEPSQ_JITTER_EPSILON_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_JITTER_EPSILON_LEN ); +REG64_FLD( MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LOCAL_NODE_EPSILON ); +REG64_FLD( MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LOCAL_NODE_EPSILON_LEN ); +REG64_FLD( MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON , 16 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NEAR_NODAL_EPSILON ); +REG64_FLD( MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NEAR_NODAL_EPSILON_LEN ); +REG64_FLD( MCS_PORT02_MCEPSQ_GROUP_EPSILON , 24 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_GROUP_EPSILON ); +REG64_FLD( MCS_PORT02_MCEPSQ_GROUP_EPSILON_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_GROUP_EPSILON_LEN ); +REG64_FLD( MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON , 32 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_REMOTE_NODAL_EPSILON ); +REG64_FLD( MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_REMOTE_NODAL_EPSILON_LEN ); +REG64_FLD( MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON , 40 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_VECTOR_GROUP_EPSILON ); +REG64_FLD( MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_VECTOR_GROUP_EPSILON_LEN ); + +REG64_FLD( MCS_PORT13_MCEPSQ_JITTER_EPSILON , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_JITTER_EPSILON ); +REG64_FLD( MCS_PORT13_MCEPSQ_JITTER_EPSILON_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_JITTER_EPSILON_LEN ); +REG64_FLD( MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LOCAL_NODE_EPSILON ); +REG64_FLD( MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LOCAL_NODE_EPSILON_LEN ); +REG64_FLD( MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NEAR_NODAL_EPSILON ); +REG64_FLD( MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NEAR_NODAL_EPSILON_LEN ); +REG64_FLD( MCS_PORT13_MCEPSQ_GROUP_EPSILON , 24 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_GROUP_EPSILON ); +REG64_FLD( MCS_PORT13_MCEPSQ_GROUP_EPSILON_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_GROUP_EPSILON_LEN ); +REG64_FLD( MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON , 32 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_REMOTE_NODAL_EPSILON ); +REG64_FLD( MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_REMOTE_NODAL_EPSILON_LEN ); +REG64_FLD( MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON , 40 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_VECTOR_GROUP_EPSILON ); +REG64_FLD( MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_VECTOR_GROUP_EPSILON_LEN ); + +REG64_FLD( MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0 , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WDF_ERR_INJECT0 ); +REG64_FLD( MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WDF_ERR_INJECT0_LEN ); +REG64_FLD( MCS_PORT02_MCERRINJ_READ_ERR_INJECT0 , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_READ_ERR_INJECT0 ); +REG64_FLD( MCS_PORT02_MCERRINJ_READ_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_READ_ERR_INJECT0_LEN ); +REG64_FLD( MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0 , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WRITE_ERR_INJECT0 ); +REG64_FLD( MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WRITE_ERR_INJECT0_LEN ); +REG64_FLD( MCS_PORT02_MCERRINJ_RCMD_ERR_INJ , 12 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RCMD_ERR_INJ ); +REG64_FLD( MCS_PORT02_MCERRINJ_PF_PROMOTE_ERR_INJ , 13 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_PROMOTE_ERR_INJ ); +REG64_FLD( MCS_PORT02_MCERRINJ_READ_PAR_NOT_SEQ , 14 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_READ_PAR_NOT_SEQ ); +REG64_FLD( MCS_PORT02_MCERRINJ_RESET_KEEPER , 15 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESET_KEEPER ); + +REG64_FLD( MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0 , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WDF_ERR_INJECT0 ); +REG64_FLD( MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WDF_ERR_INJECT0_LEN ); +REG64_FLD( MCS_PORT13_MCERRINJ_READ_ERR_INJECT0 , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_READ_ERR_INJECT0 ); +REG64_FLD( MCS_PORT13_MCERRINJ_READ_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_READ_ERR_INJECT0_LEN ); +REG64_FLD( MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0 , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WRITE_ERR_INJECT0 ); +REG64_FLD( MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WRITE_ERR_INJECT0_LEN ); +REG64_FLD( MCS_PORT13_MCERRINJ_RCMD_ERR_INJ , 12 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RCMD_ERR_INJ ); +REG64_FLD( MCS_PORT13_MCERRINJ_PF_PROMOTE_ERR_INJ , 13 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_PROMOTE_ERR_INJ ); +REG64_FLD( MCS_PORT13_MCERRINJ_READ_PAR_NOT_SEQ , 14 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_READ_PAR_NOT_SEQ ); +REG64_FLD( MCS_PORT13_MCERRINJ_RESET_KEEPER , 15 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESET_KEEPER ); + +REG64_FLD( MCS_MCFGP_VALID , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_VALID ); +REG64_FLD( MCS_MCFGP_MC_CHANNELS_PER_GROUP , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_MC_CHANNELS_PER_GROUP ); +REG64_FLD( MCS_MCFGP_MC_CHANNELS_PER_GROUP_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_MC_CHANNELS_PER_GROUP_LEN ); +REG64_FLD( MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION ); +REG64_FLD( MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN ); +REG64_FLD( MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION ); +REG64_FLD( MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN ); +REG64_FLD( MCS_MCFGP_RESERVED_11_12 , 11 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_11_12 ); +REG64_FLD( MCS_MCFGP_RESERVED_11_12_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_11_12_LEN ); +REG64_FLD( MCS_MCFGP_GROUP_SIZE , 13 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_SIZE ); +REG64_FLD( MCS_MCFGP_GROUP_SIZE_LEN , 11 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_SIZE_LEN ); +REG64_FLD( MCS_MCFGP_GROUP_BASE_ADDRESS , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_BASE_ADDRESS ); +REG64_FLD( MCS_MCFGP_GROUP_BASE_ADDRESS_LEN , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_BASE_ADDRESS_LEN ); + +REG64_FLD( MCS_MCFGPA_HOLE0_VALID , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_VALID ); +REG64_FLD( MCS_MCFGPA_RESERVED_1 , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1 ); +REG64_FLD( MCS_MCFGPA_HOLE0_LOWER_ADDRESS , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_LOWER_ADDRESS ); +REG64_FLD( MCS_MCFGPA_HOLE0_LOWER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_LOWER_ADDRESS_LEN ); +REG64_FLD( MCS_MCFGPA_RESERVED_12_13 , 12 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_13 ); +REG64_FLD( MCS_MCFGPA_RESERVED_12_13_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_13_LEN ); +REG64_FLD( MCS_MCFGPA_HOLE0_UPPER_ADDRESS , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_UPPER_ADDRESS ); +REG64_FLD( MCS_MCFGPA_HOLE0_UPPER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_UPPER_ADDRESS_LEN ); +REG64_FLD( MCS_MCFGPA_HOLE1_VALID , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_VALID ); +REG64_FLD( MCS_MCFGPA_RESERVED_25 , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_25 ); +REG64_FLD( MCS_MCFGPA_HOLE1_LOWER_ADDRESS , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_LOWER_ADDRESS ); +REG64_FLD( MCS_MCFGPA_HOLE1_LOWER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_LOWER_ADDRESS_LEN ); +REG64_FLD( MCS_MCFGPA_RESERVED_36_37 , 36 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_36_37 ); +REG64_FLD( MCS_MCFGPA_RESERVED_36_37_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_36_37_LEN ); +REG64_FLD( MCS_MCFGPA_HOLE1_UPPER_ADDRESS , 38 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_UPPER_ADDRESS ); +REG64_FLD( MCS_MCFGPA_HOLE1_UPPER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_UPPER_ADDRESS_LEN ); + +REG64_FLD( MCS_MCFGPM_VALID , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_VALID ); +REG64_FLD( MCS_MCFGPM_RESERVED_1_12 , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_12 ); +REG64_FLD( MCS_MCFGPM_RESERVED_1_12_LEN , 12 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_12_LEN ); +REG64_FLD( MCS_MCFGPM_GROUP_SIZE , 13 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_SIZE ); +REG64_FLD( MCS_MCFGPM_GROUP_SIZE_LEN , 11 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_SIZE_LEN ); +REG64_FLD( MCS_MCFGPM_GROUP_BASE_ADDRESS , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_BASE_ADDRESS ); +REG64_FLD( MCS_MCFGPM_GROUP_BASE_ADDRESS_LEN , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GROUP_BASE_ADDRESS_LEN ); + +REG64_FLD( MCS_MCFGPMA_HOLE0_VALID , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_VALID ); +REG64_FLD( MCS_MCFGPMA_RESERVED_1 , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1 ); +REG64_FLD( MCS_MCFGPMA_HOLE0_LOWER_ADDRESS , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_LOWER_ADDRESS ); +REG64_FLD( MCS_MCFGPMA_HOLE0_LOWER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_LOWER_ADDRESS_LEN ); +REG64_FLD( MCS_MCFGPMA_RESERVED_12_13 , 12 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_13 ); +REG64_FLD( MCS_MCFGPMA_RESERVED_12_13_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_13_LEN ); +REG64_FLD( MCS_MCFGPMA_HOLE0_UPPER_ADDRESS , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_UPPER_ADDRESS ); +REG64_FLD( MCS_MCFGPMA_HOLE0_UPPER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE0_UPPER_ADDRESS_LEN ); +REG64_FLD( MCS_MCFGPMA_HOLE1_VALID , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_VALID ); +REG64_FLD( MCS_MCFGPMA_RESERVED_25 , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_25 ); +REG64_FLD( MCS_MCFGPMA_HOLE1_LOWER_ADDRESS , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_LOWER_ADDRESS ); +REG64_FLD( MCS_MCFGPMA_HOLE1_LOWER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_LOWER_ADDRESS_LEN ); +REG64_FLD( MCS_MCFGPMA_RESERVED_36_37 , 36 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_36_37 ); +REG64_FLD( MCS_MCFGPMA_RESERVED_36_37_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_36_37_LEN ); +REG64_FLD( MCS_MCFGPMA_HOLE1_UPPER_ADDRESS , 38 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_UPPER_ADDRESS ); +REG64_FLD( MCS_MCFGPMA_HOLE1_UPPER_ADDRESS_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_HOLE1_UPPER_ADDRESS_LEN ); + +REG64_FLD( MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR , 0 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR ); +REG64_FLD( MCS_MCFIR_MC_INTERNAL_NONRECOVERABLE_ERROR , 1 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR ); +REG64_FLD( MCS_MCFIR_POWERBUS_PROTOCOL_ERROR , 2 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_PROTOCOL_ERROR ); +REG64_FLD( MCS_MCFIR_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE , 3 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE ); +REG64_FLD( MCS_MCFIR_MULTIPLE_BAR , 4 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MULTIPLE_BAR ); +REG64_FLD( MCS_MCFIR_INVALID_ADDRESS , 5 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_INVALID_ADDRESS ); +REG64_FLD( MCS_MCFIR_HA_ILLEGAL_CONSUMER_ACCESS , 6 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS ); +REG64_FLD( MCS_MCFIR_HA_ILLEGAL_PRODUCER_ACCESS , 7 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS ); +REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT , 8 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_COMMAND_LIST_TIMEOUT ); +REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC , 9 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_COMMAND_LIST_TIMEOUT_SPEC ); +REG64_FLD( MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR , 10 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_CHANNEL_0_TIMEOUT_ERROR ); +REG64_FLD( MCS_MCFIR_CHANNEL_1_TIMEOUT_ERROR , 11 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_CHANNEL_1_TIMEOUT_ERROR ); +REG64_FLD( MCS_MCFIR_RESERVED12 , 12 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED12 ); +REG64_FLD( MCS_MCFIR_RESERVED13 , 13 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED13 ); +REG64_FLD( MCS_MCFIR_MCS_WAT , 14 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MCS_WAT ); +REG64_FLD( MCS_MCFIR_MIRROR_ACTION_OCCURRED , 15 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MIRROR_ACTION_OCCURRED ); +REG64_FLD( MCS_MCFIR_CENTAUR_SYNC_COMMAND_DETECTED , 16 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED ); +REG64_FLD( MCS_MCFIR_RESERVED17 , 17 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED17 ); +REG64_FLD( MCS_MCFIR_RESERVED18 , 18 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED18 ); +REG64_FLD( MCS_MCFIR_RESERVED19 , 19 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED19 ); +REG64_FLD( MCS_MCFIR_RESERVED20 , 20 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED20 ); +REG64_FLD( MCS_MCFIR_RESERVED21 , 21 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED21 ); +REG64_FLD( MCS_MCFIR_RESERVED22 , 22 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED22 ); +REG64_FLD( MCS_MCFIR_RESERVED23 , 23 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED23 ); +REG64_FLD( MCS_MCFIR_INTERNAL_SCOM_ERROR , 24 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( MCS_MCFIR_INTERNAL_SCOM_ERROR_CLONE , 25 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( MCS_MCFIRACT0_ACTION_0 , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ACTION_0 ); +REG64_FLD( MCS_MCFIRACT0_ACTION_0_LEN , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ACTION_0_LEN ); + +REG64_FLD( MCS_MCFIRACT1_ACTION_1 , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ACTION_1 ); +REG64_FLD( MCS_MCFIRACT1_ACTION_1_LEN , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ACTION_1_LEN ); + +REG64_FLD( MCS_MCFIRMASK_FIR_MASK , 0 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_FIR_MASK ); +REG64_FLD( MCS_MCFIRMASK_FIR_MASK_LEN , 26 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_FIR_MASK_LEN ); + +REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RETRY_LPC_LFSR_SELECT ); +REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RETRY_LPC_LFSR_SELECT_LEN ); +REG64_FLD( MCS_MCLFSR_ENABLE_READ_LFSR_DATA , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_READ_LFSR_DATA ); +REG64_FLD( MCS_MCLFSR_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR ); +REG64_FLD( MCS_MCLFSR_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR ); +REG64_FLD( MCS_MCLFSR_RESERVED515 , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED515 ); +REG64_FLD( MCS_MCLFSR_RESERVED515_LEN , 11 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED515_LEN ); + +REG64_FLD( MCS_MCMODE0_DIRECT_ATTACH_MODE , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DIRECT_ATTACH_MODE ); +REG64_FLD( MCS_MCMODE0_CENTAUR_MODE , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAUR_MODE ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_CP_ME , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_CP_ME ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_NEW_AMO , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_NEW_AMO ); +REG64_FLD( MCS_MCMODE0_CENTAURP_INBAND_IS_63 , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_INBAND_IS_63 ); +REG64_FLD( MCS_MCMODE0_SYNC_MODE , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_MODE ); +REG64_FLD( MCS_MCMODE0_ASYNC_MODE , 6 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ASYNC_MODE ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_ECRESP , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_ECRESP ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC ); +REG64_FLD( MCS_MCMODE0_ENABLE_64_128B_READ , 9 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_64_128B_READ ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_CENTAURP_CMD , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_BYPASS_CMD , 11 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_BYPASS_CMD ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_CR_SIDEBAND , 12 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_DTAG_CR , 13 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_DTAG_CR ); +REG64_FLD( MCS_MCMODE0_EN_CHARB_STALL , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_EN_CHARB_STALL ); +REG64_FLD( MCS_MCMODE0_SYNC_FENCE , 15 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_FENCE ); +REG64_FLD( MCS_MCMODE0_ECRESP_HASH_MODE , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ECRESP_HASH_MODE ); +REG64_FLD( MCS_MCMODE0_ENABLE_FIR_SPEC_ATTN , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_FIR_SPEC_ATTN ); +REG64_FLD( MCS_MCMODE0_ENABLE_FIR_HOST_ATTN , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_FIR_HOST_ATTN ); +REG64_FLD( MCS_MCMODE0_MCS_RESET_KEEPER , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_MCS_RESET_KEEPER ); +REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_SYNC , 20 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CENTAUR_SYNC ); +REG64_FLD( MCS_MCMODE0_ENABLE_EMER_THROTTLE , 21 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_EMER_THROTTLE ); +REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_CHECKSTOP_COMMAND , 22 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND ); +REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_TRACESTOP_COMMAND , 23 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND ); +REG64_FLD( MCS_MCMODE0_RESERVED24 , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED24 ); +REG64_FLD( MCS_MCMODE0_RESERVED25 , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED25 ); +REG64_FLD( MCS_MCMODE0_DISABLE_CL_AO_QUEUES , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CL_AO_QUEUES ); +REG64_FLD( MCS_MCMODE0_RESERVED27 , 27 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED27 ); +REG64_FLD( MCS_MCMODE0_FORCE_NON_INBAND_CL_FULL , 28 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_FORCE_NON_INBAND_CL_FULL ); +REG64_FLD( MCS_MCMODE0_MCMODE0_64B_WR_IS_PWRT , 29 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_MCMODE0_64B_WR_IS_PWRT ); +REG64_FLD( MCS_MCMODE0_CL_GLOBAL_DISABLE , 30 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CL_GLOBAL_DISABLE ); +REG64_FLD( MCS_MCMODE0_CL_GLOBAL_DISABLE_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CL_GLOBAL_DISABLE_LEN ); +REG64_FLD( MCS_MCMODE0_CL_FINE_DISABLE , 40 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CL_FINE_DISABLE ); +REG64_FLD( MCS_MCMODE0_CL_FINE_DISABLE_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CL_FINE_DISABLE_LEN ); +REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_64B_READ_OPS , 47 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CENTAURP_ENABLE_64B_READ_OPS ); +REG64_FLD( MCS_MCMODE0_ENABLE_PB_PERFMON_COMMAND , 48 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_PB_PERFMON_COMMAND ); +REG64_FLD( MCS_MCMODE0_SCOM_PERFMON_START_COMMAND , 49 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SCOM_PERFMON_START_COMMAND ); +REG64_FLD( MCS_MCMODE0_SCOM_PERFMON_STOP_COMMAND , 50 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SCOM_PERFMON_STOP_COMMAND ); +REG64_FLD( MCS_MCMODE0_DISABLE_PERFMON_RESET_ON_START , 51 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_PERFMON_RESET_ON_START ); +REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_START_COMMAND , 52 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND ); +REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_STOP_COMMAND , 53 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND ); +REG64_FLD( MCS_MCMODE0_RESERVED54 , 54 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED54 ); +REG64_FLD( MCS_MCMODE0_RESERVED55 , 55 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED55 ); +REG64_FLD( MCS_MCMODE0_GENERATE_MPIPL_SEQUENCE , 56 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_GENERATE_MPIPL_SEQUENCE ); +REG64_FLD( MCS_MCMODE0_RESERVED57_63 , 57 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED57_63 ); +REG64_FLD( MCS_MCMODE0_RESERVED57_63_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED57_63_LEN ); + +REG64_FLD( MCS_MCMODE1_DISABLE_HIGH_PRIORITY , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_HIGH_PRIORITY ); +REG64_FLD( MCS_MCMODE1_DISABLE_HIGH_PRIORITY_LEN , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_HIGH_PRIORITY_LEN ); +REG64_FLD( MCS_MCMODE1_DISABLE_FP_M_BIT , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_FP_M_BIT ); +REG64_FLD( MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS , 11 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CRC_ECC_BYPASS ); +REG64_FLD( MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS_LEN , 6 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN ); +REG64_FLD( MCS_MCMODE1_DISABLE_CRC_ECC_FP_BYPASS , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CRC_ECC_FP_BYPASS ); +REG64_FLD( MCS_MCMODE1_ENABLE_CRC_ECC_BPASS_NODAL_ONLY , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY ); +REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_SPEC_SOURCE_SCOPE ); +REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE_LEN , 9 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN ); +REG64_FLD( MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH , 28 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH ); +REG64_FLD( MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN ); +REG64_FLD( MCS_MCMODE1_DISABLE_ALL_SPEC_OPS , 32 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_ALL_SPEC_OPS ); +REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_OP , 33 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_SPEC_OP ); +REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_OP_LEN , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_SPEC_OP_LEN ); +REG64_FLD( MCS_MCMODE1_DISABLE_CI , 52 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CI ); +REG64_FLD( MCS_MCMODE1_DISABLE_CI_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CI_LEN ); +REG64_FLD( MCS_MCMODE1_DISABLE_COMMAND_BYPASS , 54 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_COMMAND_BYPASS ); +REG64_FLD( MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_COMMAND_BYPASS_LEN ); +REG64_FLD( MCS_MCMODE1_DISABLE_FP_COMMAND_BYPASS , 59 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_FP_COMMAND_BYPASS ); +REG64_FLD( MCS_MCMODE1_DISABLE_BYPASS_IN_READ_DATAFLOW , 60 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW ); +REG64_FLD( MCS_MCMODE1_RESERVED61_63 , 61 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED61_63 ); +REG64_FLD( MCS_MCMODE1_RESERVED61_63_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED61_63_LEN ); + +REG64_FLD( MCS_MCMODE2_FORCE_SFSTAT_ACTIVE , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_FORCE_SFSTAT_ACTIVE ); +REG64_FLD( MCS_MCMODE2_DISABLE_MDI0 , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_MDI0 ); +REG64_FLD( MCS_MCMODE2_DISABLE_MDI0_LEN , 13 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_MDI0_LEN ); +REG64_FLD( MCS_MCMODE2_DISABLE_CENTAUR_BAD_CRESP , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CENTAUR_BAD_CRESP ); +REG64_FLD( MCS_MCMODE2_ENABLE_CRC_BYPASS_ALWAYS , 15 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CRC_BYPASS_ALWAYS ); +REG64_FLD( MCS_MCMODE2_DISABLE_SHARD_PRESP_ABORT , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_SHARD_PRESP_ABORT ); +REG64_FLD( MCS_MCMODE2_DISABLE_RETRY_LOST_CLAIM , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_RETRY_LOST_CLAIM ); +REG64_FLD( MCS_MCMODE2_DOUBLE_EPSILON_LENGTH , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DOUBLE_EPSILON_LENGTH ); +REG64_FLD( MCS_MCMODE2_RESERVED19_23 , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED19_23 ); +REG64_FLD( MCS_MCMODE2_RESERVED19_23_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED19_23_LEN ); +REG64_FLD( MCS_MCMODE2_COLLISION_MODES , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_COLLISION_MODES ); +REG64_FLD( MCS_MCMODE2_COLLISION_MODES_LEN , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_COLLISION_MODES_LEN ); + +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_VALID , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_D_VALUE , 1 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_D_VALUE ); +REG64_FLD( MCS_PORT02_MCP0XLT0_12GB_ENABLE , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_12GB_ENABLE ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_M0_VALID , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_M0_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_M1_VALID , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_M1_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_S0_VALID , 9 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_S0_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_S1_VALID , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_S1_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_S2_VALID , 11 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_S2_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_B2_VALID , 12 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_B2_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID , 13 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_ROW15_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID , 14 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_ROW16_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID , 15 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT0_ROW17_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_VALID , 16 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_D_VALUE , 17 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_D_VALUE ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_M0_VALID , 21 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_M0_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_M1_VALID , 22 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_M1_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_S0_VALID , 25 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_S0_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_S1_VALID , 26 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_S1_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_S2_VALID , 27 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_S2_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_B2_VALID , 28 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_B2_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_ROW15_VALID , 29 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_ROW15_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_ROW16_VALID , 30 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_ROW16_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_ROW17_VALID , 31 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_SLOT1_ROW17_VALID ); +REG64_FLD( MCS_PORT02_MCP0XLT0_D_BIT_MAP , 35 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_D_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_D_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT0_M0_BIT_MAP , 41 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_M0_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT0_M0_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_M0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT0_M1_BIT_MAP , 47 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_M1_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT0_M1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_M1_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT0_R17_BIT_MAP , 53 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_R17_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_R17_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT0_R16_BIT_MAP , 57 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_R16_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_R16_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT0_R15_BIT_MAP , 61 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_R15_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , + SH_FLD_R15_BIT_MAP_LEN ); + +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_VALID , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_D_VALUE , 1 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_D_VALUE ); +REG64_FLD( MCS_PORT13_MCP0XLT0_12GB_ENABLE , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_12GB_ENABLE ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_M0_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_M1_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID , 9 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_S0_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID , 10 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_S1_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID , 11 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_S2_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_B2_VALID , 12 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_B2_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_ROW15_VALID , 13 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_ROW15_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_ROW16_VALID , 14 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_ROW16_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_ROW17_VALID , 15 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT0_ROW17_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_VALID , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_D_VALUE , 17 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_D_VALUE ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_M0_VALID , 21 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_M0_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_M1_VALID , 22 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_M1_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_S0_VALID , 25 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_S0_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_S1_VALID , 26 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_S1_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_S2_VALID , 27 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_S2_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_B2_VALID , 28 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_B2_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_ROW15_VALID , 29 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_ROW15_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_ROW16_VALID , 30 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_ROW16_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_ROW17_VALID , 31 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_SLOT1_ROW17_VALID ); +REG64_FLD( MCS_PORT13_MCP0XLT0_D_BIT_MAP , 35 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_D_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT0_D_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_D_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT0_M0_BIT_MAP , 41 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_M0_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT0_M0_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_M0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT0_M1_BIT_MAP , 47 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_M1_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT0_M1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_M1_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT0_R17_BIT_MAP , 53 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_R17_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT0_R17_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_R17_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT0_R16_BIT_MAP , 57 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_R16_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT0_R16_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_R16_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT0_R15_BIT_MAP , 61 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_R15_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT0_R15_BIT_MAP_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3 , + SH_FLD_R15_BIT_MAP_LEN ); + +REG64_FLD( MCS_PORT02_MCP0XLT1_S0_BIT_MAP , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_S0_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT1_S0_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_S0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT1_S1_BIT_MAP , 11 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_S1_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT1_S1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_S1_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT1_S2_BIT_MAP , 19 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_S2_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT1_S2_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_S2_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL4_BIT_MAP , 35 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL4_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL4_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL4_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL5_BIT_MAP , 43 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL5_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL5_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL5_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL6_BIT_MAP , 51 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL6_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL6_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL6_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL7_BIT_MAP , 59 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL7_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT1_COL7_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL7_BIT_MAP_LEN ); + +REG64_FLD( MCS_PORT13_MCP0XLT1_S0_BIT_MAP , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_S0_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT1_S0_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_S0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT1_S1_BIT_MAP , 11 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_S1_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT1_S1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_S1_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT1_S2_BIT_MAP , 19 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_S2_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT1_S2_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_S2_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL4_BIT_MAP , 35 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL4_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL4_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL4_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL5_BIT_MAP , 43 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL5_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL5_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL5_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL6_BIT_MAP , 51 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL6_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL6_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL6_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL7_BIT_MAP , 59 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL7_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT1_COL7_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL7_BIT_MAP_LEN ); + +REG64_FLD( MCS_PORT02_MCP0XLT2_COL8_BIT_MAP , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL8_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT2_COL8_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL8_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT2_COL9_BIT_MAP , 11 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL9_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT2_COL9_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_COL9_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP , 19 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK0_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP , 27 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK1_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK1_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP , 35 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK2_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK2_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP , 43 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP0_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP , 51 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP1_BIT_MAP ); +REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP1_BIT_MAP_LEN ); + +REG64_FLD( MCS_PORT13_MCP0XLT2_COL8_BIT_MAP , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL8_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT2_COL8_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL8_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT2_COL9_BIT_MAP , 11 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL9_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT2_COL9_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_COL9_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP , 19 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK0_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP , 27 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK1_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK1_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP , 35 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK2_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK2_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP , 43 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP0_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP0_BIT_MAP_LEN ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP , 51 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP1_BIT_MAP ); +REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_BANK_GROUP1_BIT_MAP_LEN ); + +REG64_FLD( MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_WR_USAGE , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_DYNAMIC_WR_USAGE ); +REG64_FLD( MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_PF_USAGE , 1 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_DYNAMIC_PF_USAGE ); +REG64_FLD( MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_DYNAMIC_WINDOW_SELECT ); +REG64_FLD( MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_DYNAMIC_WINDOW_SELECT_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HPC_RD_RSVD ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HPC_RD_RSVD_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD , 12 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD , 16 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_AMO_LIMIT , 22 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_AMO_LIMIT ); +REG64_FLD( MCS_PORT02_MCPERF0_AMO_LIMIT_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_AMO_LIMIT_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_PREFETCH_LIMIT , 28 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PREFETCH_LIMIT ); +REG64_FLD( MCS_PORT02_MCPERF0_PREFETCH_LIMIT_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PREFETCH_LIMIT_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_FASTPATH_LIMIT , 34 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_FASTPATH_LIMIT ); +REG64_FLD( MCS_PORT02_MCPERF0_FASTPATH_LIMIT_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_FASTPATH_LIMIT_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT , 40 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT ); +REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT , 46 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_UPPER_LIMIT ); +REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_UPPER_LIMIT_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_CL_ACTIVE , 52 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CL_ACTIVE ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_CL_ACTIVE_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CL_ACTIVE_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL , 58 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD_SEL ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD_SEL_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL , 60 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD_SEL ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD_SEL_LEN ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL , 62 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD_SEL ); +REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN ); + +REG64_FLD( MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_WR_USAGE , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_DYNAMIC_WR_USAGE ); +REG64_FLD( MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_PF_USAGE , 1 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_DYNAMIC_PF_USAGE ); +REG64_FLD( MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_DYNAMIC_WINDOW_SELECT ); +REG64_FLD( MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_DYNAMIC_WINDOW_SELECT_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HPC_RD_RSVD ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HPC_RD_RSVD_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD , 12 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_AMO_LIMIT , 22 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_AMO_LIMIT ); +REG64_FLD( MCS_PORT13_MCPERF0_AMO_LIMIT_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_AMO_LIMIT_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_PREFETCH_LIMIT , 28 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PREFETCH_LIMIT ); +REG64_FLD( MCS_PORT13_MCPERF0_PREFETCH_LIMIT_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PREFETCH_LIMIT_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_FASTPATH_LIMIT , 34 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_FASTPATH_LIMIT ); +REG64_FLD( MCS_PORT13_MCPERF0_FASTPATH_LIMIT_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_FASTPATH_LIMIT_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT , 40 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT ); +REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT , 46 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_UPPER_LIMIT ); +REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_WR_RSVD_UPPER_LIMIT_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_CL_ACTIVE , 52 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CL_ACTIVE ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_CL_ACTIVE_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CL_ACTIVE_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL , 58 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD_SEL ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HA_RSVD_SEL_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL , 60 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD_SEL ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_HTM_RSVD_SEL_LEN ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL , 62 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD_SEL ); +REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN ); + +REG64_FLD( MCS_MCPERF1_DISABLE_FASTPATH , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_FASTPATH ); +REG64_FLD( MCS_MCPERF1_RESERVED1_2 , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1_2 ); +REG64_FLD( MCS_MCPERF1_RESERVED1_2_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1_2_LEN ); +REG64_FLD( MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ , 3 , SH_UNT_MCS , + SH_ACS_SCOM_RW , SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ ); +REG64_FLD( MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ , 4 , SH_UNT_MCS , + SH_ACS_SCOM_RW , SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ ); +REG64_FLD( MCS_MCPERF1_MCPERF1_DISABLE_FASTPATH_QOS , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS ); +REG64_FLD( MCS_MCPERF1_DISABLE_CHARB_BYPASS , 6 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_CHARB_BYPASS ); +REG64_FLD( MCS_MCPERF1_DISABLE_SPEC_DISABLE_HINT_BIT , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT ); +REG64_FLD( MCS_MCPERF1_DISABLE_2K_SPEC_FILTER , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_2K_SPEC_FILTER ); +REG64_FLD( MCS_MCPERF1_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET , 9 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET ); +REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT , 10 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT ); +REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN ); +REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT , 14 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT ); +REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN ); +REG64_FLD( MCS_MCPERF1_SPEC_READ_FILTER_NO_HASH_MODE , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE ); +REG64_FLD( MCS_MCPERF1_READ_SPECULATION_DISABLE_THRESHOLD , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD ); +REG64_FLD( MCS_MCPERF1_READ_SPECULATION_DISABLE_THRESHOLD_LEN , 6 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD_LEN ); +REG64_FLD( MCS_MCPERF1_RESERVED25 , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED25 ); +REG64_FLD( MCS_MCPERF1_READ_RAMP_PERF_TRESHOLD , 26 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_READ_RAMP_PERF_TRESHOLD ); +REG64_FLD( MCS_MCPERF1_READ_RAMP_PERF_TRESHOLD_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_READ_RAMP_PERF_TRESHOLD_LEN ); +REG64_FLD( MCS_MCPERF1_ENABLE_DISABLE_PREFETCH_FOR_MIRROR_READS , 31 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_DISABLE_PREFETCH_FOR_MIRROR_READS ); +REG64_FLD( MCS_MCPERF1_PF_DROP_CNT_THRESH , 32 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_PF_DROP_CNT_THRESH ); +REG64_FLD( MCS_MCPERF1_PF_DROP_CNT_THRESH_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_PF_DROP_CNT_THRESH_LEN ); +REG64_FLD( MCS_MCPERF1_CP_RETRY_THRESH , 39 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CP_RETRY_THRESH ); +REG64_FLD( MCS_MCPERF1_CP_RETRY_THRESH_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CP_RETRY_THRESH_LEN ); +REG64_FLD( MCS_MCPERF1_RESERVED46_48 , 46 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED46_48 ); +REG64_FLD( MCS_MCPERF1_RESERVED46_48_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED46_48_LEN ); +REG64_FLD( MCS_MCPERF1_RRQ_CAPACITY_LIMIT , 49 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RRQ_CAPACITY_LIMIT ); +REG64_FLD( MCS_MCPERF1_RRQ_CAPACITY_LIMIT_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RRQ_CAPACITY_LIMIT_LEN ); +REG64_FLD( MCS_MCPERF1_WRQ_CAPACITY_LIMIT , 54 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WRQ_CAPACITY_LIMIT ); +REG64_FLD( MCS_MCPERF1_WRQ_CAPACITY_LIMIT_LEN , 6 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_WRQ_CAPACITY_LIMIT_LEN ); +REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_CMDLIST , 60 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_PF_DROP_CMDLIST ); +REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_SRQ , 61 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_PF_DROP_SRQ ); +REG64_FLD( MCS_MCPERF1_ENABLE_PREFETCH_PROMOTE , 62 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_PREFETCH_PROMOTE ); +REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP , 63 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_PF_DROP ); + +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE0 , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE0 ); +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE0_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE0_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE1 , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE1 ); +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE1_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE1_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE2 , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE2 ); +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE2_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE2_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE3 , 9 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE3 ); +REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE3_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE3_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_DISABLE_DROPABLE , 12 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_DISABLE_DROPABLE ); +REG64_FLD( MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG , 13 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_REFRESH_BLOCK_CONFIG ); +REG64_FLD( MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_REFRESH_BLOCK_CONFIG_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_SQ , 16 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_REFRESH_BLOCK_SQ ); +REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ , 17 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_REFRESH_BLOCK_NSQ ); +REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_DISP , 18 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_REFRESH_BLOCK_DISP ); +REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_19_31 , 19 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_19_31 ); +REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_19_31_LEN , 13 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_19_31_LEN ); + +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE0 , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE0 ); +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE0_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE0_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE1 , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE1 ); +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE1_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE1_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE2 , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE2 ); +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE2_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE2_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE3 , 9 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE3 ); +REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE3_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PF_DROP_VALUE3_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_DISABLE_DROPABLE , 12 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_DISABLE_DROPABLE ); +REG64_FLD( MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG , 13 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_REFRESH_BLOCK_CONFIG ); +REG64_FLD( MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_REFRESH_BLOCK_CONFIG_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_SQ , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_REFRESH_BLOCK_SQ ); +REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ , 17 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_REFRESH_BLOCK_NSQ ); +REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_DISP , 18 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_REFRESH_BLOCK_DISP ); +REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_19_31 , 19 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_19_31 ); +REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_19_31_LEN , 13 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_19_31_LEN ); + +REG64_FLD( MCS_MCSYNC_CHANNEL_SELECT , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CHANNEL_SELECT ); +REG64_FLD( MCS_MCSYNC_CHANNEL_SELECT_LEN , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_CHANNEL_SELECT_LEN ); +REG64_FLD( MCS_MCSYNC_SYNC_TYPE , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_TYPE ); +REG64_FLD( MCS_MCSYNC_SYNC_TYPE_LEN , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_TYPE_LEN ); +REG64_FLD( MCS_MCSYNC_SYNC_GO_CH0 , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_GO_CH0 ); +REG64_FLD( MCS_MCSYNC_SYNC_GO_CH1 , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_GO_CH1 ); +REG64_FLD( MCS_MCSYNC_SYNC_REPLAY_COUNT , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_REPLAY_COUNT ); +REG64_FLD( MCS_MCSYNC_SYNC_REPLAY_COUNT_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_REPLAY_COUNT_LEN ); +REG64_FLD( MCS_MCSYNC_SYNC_RESERVED , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_RESERVED ); +REG64_FLD( MCS_MCSYNC_SYNC_RESERVED_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SYNC_RESERVED_LEN ); + +REG64_FLD( MCA_MSR_CHIPMARK , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CHIPMARK ); +REG64_FLD( MCA_MSR_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CHIPMARK_LEN ); +REG64_FLD( MCA_MSR_RANK , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RANK ); +REG64_FLD( MCA_MSR_RANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RANK_LEN ); + +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1 , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD1 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD1_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2 , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD2 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD2_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD3 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD3_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD4 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD4_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5 , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD5 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD5_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6 , 24 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD6 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD6_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7 , 28 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD7 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD7_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8 , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD8 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD8_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9 , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD9 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD9_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10 , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD10 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD10_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11 , 44 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD11 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD11_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12 , 48 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD12 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD12_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13 , 52 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD13 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD13_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14 , 56 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD14 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD14_LEN ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15 , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD15 ); +REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_LRDIMM_WORD15_LEN ); + +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT ); +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_2 , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_2 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_3 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_3 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_4 , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_4 ); +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE ); +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_UE_RETRY , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DISABLE_UE_RETRY ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_7_8 , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_7_8 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_7_8_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_7_8_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_10 , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_10 ); +REG64_FLD( MCA_RECR_MBSECCQ_INT_RESET_KEEPER , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_INT_RESET_KEEPER ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_12_16 , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_12_16 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_12_16_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_12_16_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_READ_POINTER_DELAY ); +REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_EXIT_OVERRIDE , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_EXIT_OVERRIDE ); +REG64_FLD( MCA_RECR_MBSECCQ_EXIT_OVERRIDE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_22_25 , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_22_25 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_22_25_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_22_25_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_DATA_GENERATOR_OVERRIDE , 26 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE ); +REG64_FLD( MCA_RECR_MBSECCQ_DATA_GENERATOR_META_ENABLE , 27 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DATA_GENERATOR_META_ENABLE ); +REG64_FLD( MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY ); +REG64_FLD( MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY , 31 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY ); +REG64_FLD( MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_DELAY_VALID_1X , 34 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DELAY_VALID_1X ); +REG64_FLD( MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY , 35 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY ); +REG64_FLD( MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_DELAY_NONBYPASS , 37 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DELAY_NONBYPASS ); +REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_SPECIAL_ATTENTION , 38 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION ); +REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_HOST_ATTENTION , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_40_47 , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_40_47 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_40_47_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_40_47_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_USE_ADDRESS_HASH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_USE_ADDRESS_HASH ); +REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DATA_INVERSION ); +REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DATA_INVERSION_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_51 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_51 ); + +REG64_FLD( MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RUNTIME_CTR ); +REG64_FLD( MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_RUNTIME_CTR_LEN ); + +REG64_FLD( MCA_WBMGR_TAG_INFO_BUFFER_OVERRUN , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_BUFFER_OVERRUN ); +REG64_FLD( MCA_WBMGR_TAG_INFO_OVERRUN , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_OVERRUN ); +REG64_FLD( MCA_WBMGR_TAG_INFO_REL_ASYNC_PARITY_ERROR , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REL_ASYNC_PARITY_ERROR ); +REG64_FLD( MCA_WBMGR_TAG_INFO_REL_ASYNC_SEQUENCE_ERROR , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REL_ASYNC_SEQUENCE_ERROR ); +REG64_FLD( MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_PARITY_ERROR , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR ); +REG64_FLD( MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_SEQUENCE_ERROR , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR ); +REG64_FLD( MCA_WBMGR_TAG_INFO_INFORMATION , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INFORMATION ); +REG64_FLD( MCA_WBMGR_TAG_INFO_INFORMATION_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INFORMATION_LEN ); + +REG64_FLD( MCA_WDFCFG_CFG_WRITE_MODE_ECC_CHK_DIS , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS ); +REG64_FLD( MCA_WDFCFG_CFG_WRITE_MODE_ECC_COR_DIS , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS ); +REG64_FLD( MCA_WDFCFG_CFG_WDF_SERIAL_SEQ_MODE , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WDF_SERIAL_SEQ_MODE ); +REG64_FLD( MCA_WDFCFG_RESET_KEEPER , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESET_KEEPER ); +REG64_FLD( MCA_WDFCFG_MERGE_CAPACITY_LIMIT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MERGE_CAPACITY_LIMIT ); +REG64_FLD( MCA_WDFCFG_MERGE_CAPACITY_LIMIT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MERGE_CAPACITY_LIMIT_LEN ); +REG64_FLD( MCA_WDFCFG_8_11_SPARE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_8_11_SPARE ); +REG64_FLD( MCA_WDFCFG_8_11_SPARE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_8_11_SPARE_LEN ); +REG64_FLD( MCA_WDFCFG_ASYNC_INJ , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ASYNC_INJ ); +REG64_FLD( MCA_WDFCFG_ASYNC_INJ_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ASYNC_INJ_LEN ); +REG64_FLD( MCA_WDFCFG_18_31_SPARE , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_18_31_SPARE ); +REG64_FLD( MCA_WDFCFG_18_31_SPARE_LEN , 14 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_18_31_SPARE_LEN ); +REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT ); +REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN ); +REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WDF_HCA_TIMEBASE ); +REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_LEN , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN ); + +REG64_FLD( MCA_WDFDBG_DBG_SEL_IN , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_IN ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_WDF , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_WDF ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_0 , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_1 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_0 , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_1 , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_0 , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_1 , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_0 , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_1 , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_0 , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_1 , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_0 , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_1 , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_PWCTL_DEBUG , 14 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_PWCTL_DEBUG ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFMGR_DEBUG , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_WDFMGR_DEBUG ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_0 , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_WDFRD_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_1 , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_WDFRD_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_0 , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_WDFWR_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_1 , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_WDFWR_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_0 , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 ); +REG64_FLD( MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_1 , 21 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 ); + +REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE ); +REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE ); +REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_EN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN ); +REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_X8 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 ); +REG64_FLD( MCA_WECR_MBA_WRD_MODE_RESERVED_4 , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBA_WRD_MODE_RESERVED_4 ); +REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN ); + +REG64_FLD( MCA_WOF_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_FIR ); +REG64_FLD( MCA_WOF_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_FIR_LEN ); + +REG64_FLD( MCA_WRTCFG_CFG_WRITE_MODE_ECC_CHK_DIS , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS ); +REG64_FLD( MCA_WRTCFG_CFG_WRITE_MODE_ECC_COR_DIS , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS ); +REG64_FLD( MCA_WRTCFG_RESET_KEEPER , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESET_KEEPER ); +REG64_FLD( MCA_WRTCFG_SPARE , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SPARE ); +REG64_FLD( MCA_WRTCFG_ASYNC_INJ , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ASYNC_INJ ); +REG64_FLD( MCA_WRTCFG_ASYNC_INJ_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ASYNC_INJ_LEN ); + +REG64_FLD( MCA_WRTDBGMCA_MCA_DBG_SEL_IN , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCA_DBG_SEL_IN ); +REG64_FLD( MCA_WRTDBGMCA_MCA_DBG_SEL_WRT , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MCA_DBG_SEL_WRT ); +REG64_FLD( MCA_WRTDBGMCA_WBRD_DEBUG_0_SELECT , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WBRD_DEBUG_0_SELECT ); +REG64_FLD( MCA_WRTDBGMCA_WBRD_DEBUG_1_SELECT , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WBRD_DEBUG_1_SELECT ); +REG64_FLD( MCA_WRTDBGMCA_SEC_WBRD_DEBUG_0_SELECT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEC_WBRD_DEBUG_0_SELECT ); +REG64_FLD( MCA_WRTDBGMCA_SEC_WBRD_DEBUG_1_SELECT , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SEC_WBRD_DEBUG_1_SELECT ); + +REG64_FLD( MCA_WRTDBGNEST_NEST_DBG_SEL_IN , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NEST_DBG_SEL_IN ); +REG64_FLD( MCA_WRTDBGNEST_NEST_DBG_SEL_WRT , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_NEST_DBG_SEL_WRT ); +REG64_FLD( MCA_WRTDBGNEST_WBMGR_DBG_0_SELECT , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WBMGR_DBG_0_SELECT ); +REG64_FLD( MCA_WRTDBGNEST_WBMGR_DBG_1_SELECT , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WBMGR_DBG_1_SELECT ); +REG64_FLD( MCA_WRTDBGNEST_WRCNTL_DBG_SELECT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WRCNTL_DBG_SELECT ); + +REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE , 0 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW0_ERR_TYPE ); +REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW0_ERR_TYPE_LEN ); +REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW0_SYNDROME ); +REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW0_SYNDROME_LEN ); +REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE , 16 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW1_ERR_TYPE ); +REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW1_ERR_TYPE_LEN ); +REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME , 24 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW1_SYNDROME ); +REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW1_SYNDROME_LEN ); +REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE , 32 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW2_ERR_TYPE ); +REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW2_ERR_TYPE_LEN ); +REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME , 40 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW2_SYNDROME ); +REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW2_SYNDROME_LEN ); +REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE , 48 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW3_ERR_TYPE ); +REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW3_ERR_TYPE_LEN ); +REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME , 56 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW3_SYNDROME ); +REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , + SH_FLD_DW3_SYNDROME_LEN ); + +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE , 0 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW0_ERR_TYPE ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW0_ERR_TYPE_LEN ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW0_SYNDROME ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW0_SYNDROME_LEN ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE , 16 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW1_ERR_TYPE ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW1_ERR_TYPE_LEN ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME , 24 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW1_SYNDROME ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW1_SYNDROME_LEN ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE , 32 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW2_ERR_TYPE ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW2_ERR_TYPE_LEN ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME , 40 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW2_SYNDROME ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW2_SYNDROME_LEN ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE , 48 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW3_ERR_TYPE ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW3_ERR_TYPE_LEN ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME , 56 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW3_SYNDROME ); +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , + SH_FLD_DW3_SYNDROME_LEN ); + +#endif + |
