diff options
| author | Ben Gass <bgass@us.ibm.com> | 2015-11-12 10:05:09 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-02-22 15:17:37 -0600 |
| commit | 28055d6525354ecb369ed2ee2ca10c9149770394 (patch) | |
| tree | da1f537c6245cbe8461abb375b0aa7231e5f8704 /src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H | |
| parent | f00bb28d5cf9f95399629e6a3bf9f5a1515d2dbd (diff) | |
| download | talos-hostboot-28055d6525354ecb369ed2ee2ca10c9149770394.tar.gz talos-hostboot-28055d6525354ecb369ed2ee2ca10c9149770394.zip | |
Regenerated header files from e9029
New figdb, added map file from consts to regs
Change-Id: I3f67469fc4910bff27b183e52a41816b0899729e
Original-Change-Id: Ie31dacbb66ac374bb24adb2f62b09725ac30c56a
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21994
Tested-by: Jenkins Server
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24597
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H | 4316 |
1 files changed, 3149 insertions, 1167 deletions
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H index 9452f4a05..74367cc31 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H @@ -72,16 +72,42 @@ REG64_FLD( MCA_AAER_TAG_ECC , 0 , SH_UN REG64_FLD( MCA_AAER_TAG_ECC_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_TAG_ECC_LEN ); -REG64_FLD( MCA_ACTION0_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_ACTION0_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_FIR ); -REG64_FLD( MCA_ACTION0_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_ACTION0_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_FIR_LEN ); -REG64_FLD( MCA_ACTION1_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_ACTION1_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_FIR ); -REG64_FLD( MCA_ACTION1_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_ACTION1_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_FIR_LEN ); +REG64_FLD( MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( MCA_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( MCA_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + +REG64_FLD( MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE ); REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -90,8 +116,8 @@ REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE , 2 , SH_UN SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE ); REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CCS_ARRAY_UE_ERR_INJ ); -REG64_FLD( MCBIST_CCSARRERRINJQ_CS_CHIP_ID_2N_MODE , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_CS_CHIP_ID_2N_MODE ); +REG64_FLD( MCBIST_CCSARRERRINJQ_RESERVED_4 , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_4 ); REG64_FLD( MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_DISABLE_2N_MODE ); REG64_FLD( MCBIST_CCSARRERRINJQ_RESERVED_6_14 , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -3345,6 +3371,193 @@ REG64_FLD( MCBIST_CCS_STATQ_FAIL_TYPE_LEN , 3 , SH_UN SH_FLD_FAIL_TYPE_LEN ); REG64_FLD( MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_MCBIST_SUBTEST_IP ); +REG64_FLD( MCBIST_CCS_STATQ_FAIL_RCD , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FAIL_RCD ); + +REG64_FLD( MCA_CERR0_RECR_PE , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RECR_PE ); +REG64_FLD( MCA_CERR0_MSR_PE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_MSR_PE ); +REG64_FLD( MCA_CERR0_EICR_PE , 13 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EICR_PE ); +REG64_FLD( MCA_CERR0_HWMSX_PE , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HWMSX_PE ); +REG64_FLD( MCA_CERR0_HWMSX_PE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HWMSX_PE_LEN ); +REG64_FLD( MCA_CERR0_FWMSX_PE , 24 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FWMSX_PE ); +REG64_FLD( MCA_CERR0_FWMSX_PE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_FWMSX_PE_LEN ); +REG64_FLD( MCA_CERR0_WECR_PE , 40 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WECR_PE ); +REG64_FLD( MCA_CERR0_AACR_PE , 41 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_AACR_PE ); +REG64_FLD( MCA_CERR0_AADR_PE , 42 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_AADR_PE ); +REG64_FLD( MCA_CERR0_AAER_PE , 43 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_AAER_PE ); +REG64_FLD( MCA_CERR0_MCBCM_PE , 44 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_MCBCM_PE ); +REG64_FLD( MCA_CERR0_WDFCFG_PE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WDFCFG_PE ); +REG64_FLD( MCA_CERR0_WRTCFG_PE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRTCFG_PE ); + +REG64_FLD( MCA_CERR1_READ_ECC_CONTROL_PARITY_ERROR , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_READ_ECC_CONTROL_PARITY_ERROR ); +REG64_FLD( MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR , 1 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR ); +REG64_FLD( MCA_CERR1_READ_ECC_ECCPIPE_PARITY_ERROR , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_READ_ECC_ECCPIPE_PARITY_ERROR ); +REG64_FLD( MCA_CERR1_PHY_PARITY_HOLD_OUT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PHY_PARITY_HOLD_OUT ); +REG64_FLD( MCA_CERR1_WDF_ASYNC_ERROR , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WDF_ASYNC_ERROR ); +REG64_FLD( MCA_CERR1_WDF_BUFFER_CE , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WDF_BUFFER_CE ); +REG64_FLD( MCA_CERR1_WDF_BUFFER_UE , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WDF_BUFFER_UE ); +REG64_FLD( MCA_CERR1_WDF_BUFFER_SUE , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WDF_BUFFER_SUE ); +REG64_FLD( MCA_CERR1_WRT_BUFFER_CE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRT_BUFFER_CE ); +REG64_FLD( MCA_CERR1_WRT_BUFFER_UE , 18 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRT_BUFFER_UE ); +REG64_FLD( MCA_CERR1_WRT_BUFFER_SUE , 19 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRT_BUFFER_SUE ); +REG64_FLD( MCA_CERR1_READ_CONTROL_OVERFLOW_ERROR , 24 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_READ_CONTROL_OVERFLOW_ERROR ); +REG64_FLD( MCA_CERR1_WRITE_ECC_DATAPATH_ERROR , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ECC_DATAPATH_ERROR ); + +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_ENABLE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_ENABLE ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01 , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_ASYNC_PORT01 ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01_LEN , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_ASYNC_PORT01_LEN ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_ASYNC_PORT23 ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23_LEN , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_ASYNC_PORT23_LEN ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01 , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_MCBIST01 ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01_LEN , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_MCBIST01_LEN ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23 , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_MCBIST23 ); +REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23_LEN , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_PICK_MCBIST23_LEN ); +REG64_FLD( MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_TRIGGER , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_SET_WAT_EXT_TRIGGER ); +REG64_FLD( MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_RESET , 46 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_SET_WAT_EXT_RESET ); +REG64_FLD( MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_ARM , 47 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_SCOM_SET_WAT_EXT_ARM ); + +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_ENABLE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_ENABLE ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_EVENT_TO_INT ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT_LEN , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_EVENT_TO_INT_LEN ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_TRIGGER_SEL ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_TRIGGER_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_RESET_SEL ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_RESET_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL , 43 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_ARM_SEL ); +REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXT_ARM_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG1Q_RESERVED_63 , 63 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_63 ); + +REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT0_SEL ); +REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT0_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT1_SEL ); +REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT1_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL , 40 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT2_SEL ); +REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT2_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG2Q_RESERVED_60_63 , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63 ); +REG64_FLD( MCBIST_DBGCFG2Q_RESERVED_60_63_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_63_LEN ); + +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT3_SEL ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_LOC_EVENT3_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT0_SEL ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT0_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT1_SEL ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT1_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL , 26 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT2_SEL ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT2_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL , 29 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT3_SEL ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_GLOB_EVENT3_SEL_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_OUTPUT_PULSE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_OUTPUT_PULSE ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE , 33 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE , 41 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE ); +REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN ); +REG64_FLD( MCBIST_DBGCFG3Q_RESERVED_45_47 , 45 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_45_47 ); +REG64_FLD( MCBIST_DBGCFG3Q_RESERVED_45_47_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_45_47_LEN ); + +REG64_FLD( MCA_DBGR_ECC_DEBUG_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_DEBUG_ENABLE ); +REG64_FLD( MCA_DBGR_ECC_DEBUG_CHUNK_SELECT , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_DEBUG_CHUNK_SELECT ); +REG64_FLD( MCA_DBGR_ECC_DEBUG_CHUNK_SELECT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_DEBUG_CHUNK_SELECT_LEN ); +REG64_FLD( MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_DEBUG_PRIMARY_SELECT ); +REG64_FLD( MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_DEBUG_PRIMARY_SELECT_LEN ); +REG64_FLD( MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_DEBUG_SECONDARY_SELECT ); +REG64_FLD( MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_DEBUG_SECONDARY_SELECT_LEN ); +REG64_FLD( MCA_DBGR_ECC_WAT_ENABLE , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WAT_ENABLE ); +REG64_FLD( MCA_DBGR_ECC_WAT_ACTION_SELECT , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WAT_ACTION_SELECT ); +REG64_FLD( MCA_DBGR_ECC_WAT_SOURCE , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WAT_SOURCE ); +REG64_FLD( MCA_DBGR_ECC_WAT_SOURCE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ECC_WAT_SOURCE_LEN ); +REG64_FLD( MCA_DBGR_READ_DEBUG_SELECT , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_READ_DEBUG_SELECT ); +REG64_FLD( MCA_DBGR_READ_DEBUG_SELECT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_READ_DEBUG_SELECT_LEN ); REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_0_11 ); @@ -3382,6 +3595,28 @@ REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15 , 60 , SH_UN REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_12_15_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR0_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ADR1_DLL_COMPARE_OUT ); + REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01 ); REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -3822,62 +4057,62 @@ REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR12_ADR13 , 54 , SH_U REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR14_ADR15 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DI_ADR14_ADR15 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN ); + SH_ACS_SCOM , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC ); + SH_ACS_SCOM , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_FRZSULV ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR0_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN ); + SH_ACS_SCOM , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC ); + SH_ACS_SCOM , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_FRZSULV ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ADR1_CAL_ERROR_FINE ); REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -3926,10 +4161,10 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ATEST_SEL_0 , 52 , SH_FLD_ADR0_ATEST_SEL_0 ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ATEST_SEL_0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_ATEST_SEL_0_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3 , 59 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_INTERP_SIG_SLEW_0_3 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_0_3_LEN , 4 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR0_INTERP_SIG_SLEW_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_INTERP_SIG_SLEW ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_INTERP_SIG_SLEW_LEN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ANALOG_WRAPON , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_ANALOG_WRAPON ); @@ -3941,10 +4176,10 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ATEST_SEL_0 , 52 , SH_FLD_ADR1_ATEST_SEL_0 ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ATEST_SEL_0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_ATEST_SEL_0_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3 , 59 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_INTERP_SIG_SLEW_0_3 ); -REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_0_3_LEN , 4 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_ADR1_INTERP_SIG_SLEW_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_INTERP_SIG_SLEW ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_INTERP_SIG_SLEW_LEN ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ANALOG_WRAPON , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_ANALOG_WRAPON ); @@ -3964,6 +4199,8 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC , 56 SH_FLD_ADR0_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR0_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_COMPCON_DC ); @@ -3981,6 +4218,8 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC , 56 SH_FLD_ADR1_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR1_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_SEL0 ); @@ -4624,8 +4863,6 @@ REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET , 59 , REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_TARGET_PR_OFFSET_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_ADR0_ENABLE ); REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -4643,8 +4880,6 @@ REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_POS_EDGE_ALIGN , 60 , REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_ADR1_ENABLE ); REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -4672,10 +4907,6 @@ REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS , SH_ACS_SCOM_RO , SH_FLD_ADR0_SLEW_DONE_STATUS ); REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ADR0_SLEW_DONE_STATUS_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_RESERVED_60_63 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ADR0_RESERVED_60_63 ); -REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_RESERVED_60_63_LEN , 4 , SH_UNT_MCA , - SH_ACS_SCOM_RO , SH_FLD_ADR0_RESERVED_60_63_LEN ); REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ADR1_ROT ); @@ -4687,10 +4918,6 @@ REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS , SH_ACS_SCOM_RO , SH_FLD_ADR1_SLEW_DONE_STATUS ); REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ADR1_SLEW_DONE_STATUS_LEN ); -REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_RESERVED_60_63 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ADR1_RESERVED_60_63 ); -REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_RESERVED_60_63_LEN , 4 , SH_UNT_MCA , - SH_ACS_SCOM_RO , SH_FLD_ADR1_RESERVED_60_63_LEN ); REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CNTL ); @@ -4723,6 +4950,12 @@ REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL_LEN , 5 , SH_UN SH_FLD_DEBUG_BUS_SEL_LEN ); REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_ADR_SLAVE_SEL , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR_SLAVE_SEL ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_BUS_SEL2 ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_BUS_SEL2_LEN ); +REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_LOW_PROBE_TRACE_GATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_LOW_PROBE_TRACE_GATE ); REG64_FLD( MCA_DDRPHY_APB_ERROR_MASK0_P0_INVALID_ADDRESS_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_INVALID_ADDRESS_MASK ); @@ -4746,14 +4979,14 @@ REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET4 , 52 , SH_UN SH_FLD_ERR_SET4 ); REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET5 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ERR_SET5 ); -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP18 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ERR_FSM_DP18 ); -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP18_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ERR_FSM_DP18_LEN ); -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP18 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ERR_REG_DP18 ); -REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP18_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ERR_REG_DP18_LEN ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_FSM_DP16 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_FSM_DP16_LEN ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP16 , 59 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_REG_DP16 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_REG_DP16_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ERR_REG_DP16_LEN ); REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_ERR_STATUS0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PC_ERR_STATUS0 ); @@ -4764,384 +4997,406 @@ REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR , 53 , SH_UN REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PC_INIT_CAL_ERR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_NRE_ERR_REG_DP16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_NRE_ERR_REG_DP16 ); +REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_NRE_ERR_REG_DP16_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_NRE_ERR_REG_DP16_LEN ); + +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESET_0 ); +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_HOLD_0 ); +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_0 ); +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_0_LEN ); +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESET_1 ); +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_HOLD_1 ); +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_1 ); +REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S0ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S0ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S0ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S0ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S0ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S0ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S0ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S0ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_S1ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_S1ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S1ACENSLICENDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S1ACENSLICENDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S1ACENSLICEPDRV_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S1ACENSLICEPDRV_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S1ACENSLICEPTERM_DC ); -REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_S1ACENSLICEPTERM_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_1_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_1_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_0_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_0_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_0_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_0_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_1_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_1_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_1_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_1_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_1_3_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_0_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_0_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_0_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_NIB_3_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_3_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_0_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_0_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB_1_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_NIB_1_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_IND , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_0_2_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_0_2_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_50_52 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_50_52 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_50_52_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_50_52_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_0_2_DQSEL_RES_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP , 56 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_CAP ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_IND , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_1_3_DQSEL_IND ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_IND_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB_1_3_DQSEL_IND_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_58_60 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_58_60 ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_RESERVED_58_60_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_RESERVED_58_60_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES , 61 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_RES ); -REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_NIB_1_3_DQSEL_RES_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0_01_DIR_15 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5604,6 +5859,116 @@ REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N2 , 62 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N3 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_MRS_CMD_N3 ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DLL_COMPARE_OUT ); + +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_ADJUST ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_ADJUST_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CORRECT_EN , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_CORRECT_EN ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ITER_A , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_ITER_A ); +REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_COMPARE_OUT , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DLL_COMPARE_OUT ); + REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_HS_PROBE_A ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5614,7 +5979,7 @@ REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B_LEN , 6 , SH_UN SH_FLD_01_HS_PROBE_B_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RD ); -REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RD_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5627,7 +5992,7 @@ REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B_LEN , 6 , SH_UN SH_FLD_01_HS_PROBE_B_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RD ); -REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RD_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5640,7 +6005,7 @@ REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B_LEN , 6 , SH_UN SH_FLD_23_HS_PROBE_B_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RD ); -REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RD_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5653,7 +6018,7 @@ REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B_LEN , 6 , SH_UN SH_FLD_23_HS_PROBE_B_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RD ); -REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RD_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5666,7 +6031,7 @@ REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B_LEN , 6 , SH_UN SH_FLD_4_HS_PROBE_B_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RD ); -REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RD_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -5754,79 +6119,79 @@ REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3 , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_QUAD3_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DIGITAL_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_BUMP ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_TRIG_PERIOD ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CNTL_POL ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CNTL_SRC ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RESERVED_56_63 ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RESERVED_56_63_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DIGITAL_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_BUMP ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_TRIG_PERIOD ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CNTL_POL ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CNTL_SRC ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RESERVED_56_63 ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RESERVED_56_63_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DIGITAL_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_BUMP ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_TRIG_PERIOD ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CNTL_POL ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CNTL_SRC ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RESERVED_56_63 ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RESERVED_56_63_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DIGITAL_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_BUMP ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_TRIG_PERIOD ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CNTL_POL ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CNTL_SRC ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RESERVED_56_63 ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RESERVED_56_63_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_DIGITAL_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_DIGITAL_EN ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_BUMP , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_BUMP ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_TRIG_PERIOD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_TRIG_PERIOD ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_POL , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_CNTL_POL ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_SRC , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_CNTL_SRC ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_RESERVED_56_63 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RESERVED_56_63 ); -REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , +REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_RESERVED_56_63_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RESERVED_56_63_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM , @@ -5894,390 +6259,380 @@ REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR , 58 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_ERROR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , - SH_ACS_SCOM_RW , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_ACS_SCOM , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_RESET ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE , 49 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_INIT_RXDLL_CAL_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP , 50 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC , 53 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC , 59 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_EN_DRIVER_INVFB_DC ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_FRZSULV , 60 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_FRZSULV ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_GOOD , 61 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_GOOD ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_ERROR ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR_FINE , 63 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_CAL_ERROR_FINE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL0_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL0_3_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_DRVREN_MODE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_TUNEATST , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TUNEATST ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL1_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL1_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL1_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL1_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_1_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_1_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_ATEST_SEL_1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATEST_SEL_1 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_ATEST_SEL_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATEST_SEL_1_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_S0INSDLYTAP ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_S1INSDLYTAP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TUNEATST_1 ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL0_0_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL0_0_3_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_DRVREN_MODE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TUNEATST_0 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL1_0_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL1_0_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_HS_DLLMUX_SEL1_0_3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_0_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_0_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_HS_DLLMUX_SEL_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_ATEST_SEL_0 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATEST_SEL_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_ATEST_SEL_0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_ATEST_SEL_0_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_S0INSDLYTAP ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_S1INSDLYTAP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_TUNEATST , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_TUNEATST ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL0_0_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL0_0_3_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_DRVREN_MODE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TUNEATST_0 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL1_0_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL1_0_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL1_0_3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_0_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_0_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_1_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_1_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_ATEST_SEL_0_1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATEST_SEL_0_1 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_ATEST_SEL_0_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATEST_SEL_0_1_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_S0INSDLYTAP ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_S1INSDLYTAP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TUNEATST_1 ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL0_0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL0_0 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL0_0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL0_0_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_DRVREN_MODE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TUNEATST_0 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL1_0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL1_0 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL1_0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_HS_DLLMUX_SEL1_0_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_0_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_0_0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_1_0 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_HS_DLLMUX_SEL_1_0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_ATEST_SEL_0_1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATEST_SEL_0_1 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_ATEST_SEL_0_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_ATEST_SEL_0_1_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_S0INSDLYTAP ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_S1INSDLYTAP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_TUNEATST_1 ); - -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_HS_DLLMUX_SEL0_0_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_HS_DLLMUX_SEL0_0_3_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_DRVREN_MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_DRVREN_MODE ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_TUNEATST_0 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TUNEATST_0 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL1_0_3 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_HS_DLLMUX_SEL1_0_3 ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_HS_DLLMUX_SEL1_0_3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL_0_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL_0_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL_1_0_3 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_HS_DLLMUX_SEL_1_0_3_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_ATEST_SEL_0_1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ATEST_SEL_0_1 ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_ATEST_SEL_0_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_ATEST_SEL_0_1_LEN ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S0INSDLYTAP , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_S0INSDLYTAP ); REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S1INSDLYTAP , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_S1INSDLYTAP ); -REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_TUNEATST_1 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_TUNEATST_1 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER ); @@ -6485,6 +6840,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_COMPCON_DC ); @@ -6502,6 +6861,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_COMPCON_DC ); @@ -6519,6 +6882,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_COMPCON_DC ); @@ -6536,6 +6903,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RXREG_COMPCON_DC ); @@ -6553,6 +6924,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC , 56 , SH_ SH_FLD_4_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_COMPCON_DC ); @@ -6570,6 +6945,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_COMPCON_DC ); @@ -6587,6 +6966,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_COMPCON_DC ); @@ -6604,6 +6987,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_COMPCON_DC ); @@ -6621,6 +7008,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RXREG_COMPCON_DC ); @@ -6638,6 +7029,10 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC , 56 , SH_ SH_FLD_4_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_DRVREN_MODE ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CAL_CKTS_ACTIVE ); REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DQS ); @@ -8794,54 +9189,49 @@ REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_INTERP_SIG_SLEW , 48 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_INTERP_SIG_SLEW_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_INTERP_SIG_SLEW_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_EN_N_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_0_01_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_EN_N_WR_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_EN_N_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_1_01_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_EN_N_WR_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_EN_N_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_2_23_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_EN_N_WR_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_EN_N_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_3_23_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_EN_N_WR_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_4_4_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_EN_N_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_NFET_SLICE_P0_4_4_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_EN_N_WR_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_EN_P_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_0_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_EN_P_WR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_EN_N_WR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_EN_P_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_1_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_EN_P_WR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_EN_P_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_2_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_EN_P_WR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_EN_N_WR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_EN_P_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_3_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_EN_P_WR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_4_4_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_N_WR ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_EN_N_WR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_EN_P_WR ); -REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_SLICE_P0_4_4_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_EN_P_WR_LEN ); REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -8869,6 +9259,51 @@ REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR , 49 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_EN_P_WR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_A ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_B ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_B_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_A ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_B ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_SEL_B_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_A ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_B ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_B_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_A ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_B ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_SEL_B_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SEL_A ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SEL_A_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SEL_B ); +REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_SEL_B_LEN ); + REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_MEMINTD00 ); REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -9417,10 +9852,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR , 53 , SH_UN SH_FLD_01_DQS_ALIGN_CNTR ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_DQS_ALIGN_CNTR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_DQS_ALIGN_ITR_CNTR ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_DQS_ALIGN_ITR_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ITERATION_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ITERATION_CNTR_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_DQS_ALIGN_SM ); @@ -9430,10 +9865,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR , 53 , SH_UN SH_FLD_01_DQS_ALIGN_CNTR ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_01_DQS_ALIGN_CNTR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_DQS_ALIGN_ITR_CNTR ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_DQS_ALIGN_ITR_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ITERATION_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_ITERATION_CNTR_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_DQS_ALIGN_SM ); @@ -9443,10 +9878,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR , 53 , SH_UN SH_FLD_23_DQS_ALIGN_CNTR ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_DQS_ALIGN_CNTR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_DQS_ALIGN_ITR_CNTR ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_DQS_ALIGN_ITR_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ITERATION_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ITERATION_CNTR_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_DQS_ALIGN_SM ); @@ -9456,10 +9891,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR , 53 , SH_UN SH_FLD_23_DQS_ALIGN_CNTR ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_23_DQS_ALIGN_CNTR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_DQS_ALIGN_ITR_CNTR ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_DQS_ALIGN_ITR_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ITERATION_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_ITERATION_CNTR_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_DQS_ALIGN_SM ); @@ -9469,10 +9904,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR , 53 , SH_UN SH_FLD_4_DQS_ALIGN_CNTR ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_DQS_ALIGN_CNTR_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_ITR_CNTR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_DQS_ALIGN_ITR_CNTR ); -REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_ITR_CNTR_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_DQS_ALIGN_ITR_CNTR_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ITERATION_CNTR ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_ITERATION_CNTR_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_CALIBRATE_BIT ); @@ -9482,6 +9917,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD , 51 , SH_UN SH_FLD_01_DQS_ALIGN_QUAD ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG , 53 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_QUAD_CONFIG ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_QUAD_CONFIG_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_OPERATE_MODE ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , @@ -9503,6 +9942,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD , 51 , SH_UN SH_FLD_01_DQS_ALIGN_QUAD ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG , 53 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_QUAD_CONFIG ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_01_DQS_QUAD_CONFIG_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_01_OPERATE_MODE ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , @@ -9524,6 +9967,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD , 51 , SH_UN SH_FLD_23_DQS_ALIGN_QUAD ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG , 53 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_QUAD_CONFIG ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_QUAD_CONFIG_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_OPERATE_MODE ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , @@ -9545,6 +9992,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD , 51 , SH_UN SH_FLD_23_DQS_ALIGN_QUAD ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG , 53 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_QUAD_CONFIG ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_23_DQS_QUAD_CONFIG_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_23_OPERATE_MODE ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , @@ -9566,6 +10017,10 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD , 51 , SH_UN SH_FLD_4_DQS_ALIGN_QUAD ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_DQS_ALIGN_QUAD_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG , 53 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DQS_QUAD_CONFIG ); +REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_4_DQS_QUAD_CONFIG_LEN ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE , 56 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_4_OPERATE_MODE ); REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , @@ -10234,6 +10689,146 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_DRIFT_ERROR , 62 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_MIN_EYE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_MIN_EYE ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB0 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB1 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB2 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB3 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_NIB3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_0_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_0_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_1_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_1_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_2_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_2_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_3_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_3_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_4_4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_DONE_P0_4_4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_4_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEN ); + REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_QUAD0_CLK16 ); REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -12614,6 +13209,31 @@ REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7 , 57 , REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_OFFSET7_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4 ); +REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_LEN ); + REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RD ); REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -14939,8 +15559,6 @@ REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_READ_CENTERING_MODE , 62 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_READ_CENTERING_MODE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_READ_CENTERING_MODE_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -14958,8 +15576,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -14977,8 +15593,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -14996,8 +15610,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -15015,8 +15627,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -15034,8 +15644,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -15053,8 +15661,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -15072,8 +15678,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -15091,8 +15695,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -15110,8 +15712,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_POS_EDGE_ALIGN , 60 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_CONTINUOUS_UPDATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_CONTINUOUS_UPDATE ); -REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_ENABLE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_ROT_OVERRIDE ); REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -15194,146 +15794,6 @@ REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1 , 57 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_4_ROT1_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB0 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB0_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB1 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_0_01_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB1_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB0 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB0_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB1 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_1_01_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB1_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB0 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB0_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB1 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_2_23_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB1_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB0 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB0_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB1 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_3_23_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB1_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB0 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB0_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB0_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB1 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE0_DAC_P0_4_4_NIB1_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB1_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB2 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB2_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB3 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_0_01_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB3_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB2 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB2_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB3 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_1_01_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_NIB3_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB2 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB2_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB3 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_2_23_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB3_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB2 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB2_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB3 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_3_23_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_NIB3_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB2 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB2 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB2_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB2_LEN ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB3 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB3 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_BYTE1_DAC_P0_4_4_NIB3_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_NIB3_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_0_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_0_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_1_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_1_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_01_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_2_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_2_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_3_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_3_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_23_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_4_4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_DONE_P0_4_4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_4_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_0_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_0_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_1_01 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_1_01_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_01_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_2_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_2_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_3_23 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_3_23_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_23_LEN ); - -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_4_4 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4 ); -REG64_FLD( MCA_DDRPHY_DP16_VREF_CAL_EN_P0_4_4_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_4_LEN ); - REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_QUAD0_CLK16 ); REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK16 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -16489,12 +16949,795 @@ REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK22 , 55 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_ZERO_DETECTED , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_ZERO_DETECTED ); -REG64_FLD( MCA_DDRPHY_PC_ADR_DLL_CAL_STATUS_P0_GOOD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_GOOD ); -REG64_FLD( MCA_DDRPHY_PC_ADR_DLL_CAL_STATUS_P0_ERROR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ERROR ); -REG64_FLD( MCA_DDRPHY_PC_ADR_DLL_CAL_STATUS_P0_ERROR_FINE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ERROR_FINE ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_1D_CHICKEN_SWITCH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_1D_CHICKEN_SWITCH ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_RUN_FULL_1D , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RUN_FULL_1D ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_2D_SMALL_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_2D_SMALL_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_3D_BIG_STEP_VAL , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_3D_BIG_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_3D_BIG_STEP_VAL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_3D_BIG_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_BITS_TO_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_BITS_TO_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_NO_INC_COMP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_NO_INC_COMP_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_1D_CHICKEN_SWITCH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_1D_CHICKEN_SWITCH ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_RUN_FULL_1D , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RUN_FULL_1D ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_2D_SMALL_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_2D_SMALL_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_3D_BIG_STEP_VAL , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_3D_BIG_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_3D_BIG_STEP_VAL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_3D_BIG_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_BITS_TO_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_BITS_TO_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_NO_INC_COMP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_NO_INC_COMP_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_1D_CHICKEN_SWITCH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_1D_CHICKEN_SWITCH ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_RUN_FULL_1D , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RUN_FULL_1D ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_2D_SMALL_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_3D_BIG_STEP_VAL , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_3D_BIG_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_3D_BIG_STEP_VAL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_3D_BIG_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_BITS_TO_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_NO_INC_COMP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_1D_CHICKEN_SWITCH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_1D_CHICKEN_SWITCH ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_RUN_FULL_1D , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RUN_FULL_1D ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_2D_SMALL_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_3D_BIG_STEP_VAL , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_3D_BIG_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_3D_BIG_STEP_VAL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_3D_BIG_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_BITS_TO_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_NO_INC_COMP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_1D_CHICKEN_SWITCH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_1D_CHICKEN_SWITCH ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_RUN_FULL_1D , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RUN_FULL_1D ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_2D_SMALL_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_2D_SMALL_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_3D_BIG_STEP_VAL , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_3D_BIG_STEP_VAL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_3D_BIG_STEP_VAL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_3D_BIG_STEP_VAL_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_BITS_TO_SKIP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_BITS_TO_SKIP_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_NO_INC_COMP ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_NO_INC_COMP_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_SELECT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SELECT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_CROSSOVER ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_CROSSOVER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_SINGLE_RANGE_MAX ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_SINGLE_RANGE_MAX_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_SELECT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SELECT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_CROSSOVER ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_CROSSOVER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_SINGLE_RANGE_MAX ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_SINGLE_RANGE_MAX_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_SELECT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SELECT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_CROSSOVER ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_CROSSOVER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_SINGLE_RANGE_MAX ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_SELECT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SELECT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_CROSSOVER ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_CROSSOVER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_SINGLE_RANGE_MAX ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_SELECT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RANGE_SELECT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RANGE_CROSSOVER ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RANGE_CROSSOVER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_SINGLE_RANGE_MAX ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_SINGLE_RANGE_MAX_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_WRRDREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_WRRDREQ_CNT_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_WRRDREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_WRRDREQ_CNT_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_WRRDREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_WRRDREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_WRRDREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_WRRDREQ_CNT_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_VREFREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_VREFREQ_CNT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_CUR ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_CUR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_VREFREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_NUM_VREFREQ_CNT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_CUR ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_CUR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_VREFREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_CUR ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_CUR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_VREFREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_CUR ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_CUR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_VREFREQ_CNT ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_NUM_VREFREQ_CNT_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_CUR ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_CUR_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_CTR_RANGE_SEL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_CTR_RANGE_SEL ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM0_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM1 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM1_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_VALUE_DRAM3_LEN ); + +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM2 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2 , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM2_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RANGE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3 ); +REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_VALUE_DRAM3_LEN ); REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PERIODIC ); @@ -16583,12 +17826,18 @@ REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS6_INIT_CAL_VALUE , 54 , SH_UN REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS7_INIT_CAL_VALUE , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CS7_INIT_CAL_VALUE ); -REG64_FLD( MCA_DDRPHY_PC_DP16_DLL_CAL_STATUS_P0_DP_GOOD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_DDRPHY_PC_DLL_CAL_STATUS_P0_DP_GOOD , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_DP_GOOD ); -REG64_FLD( MCA_DDRPHY_PC_DP16_DLL_CAL_STATUS_P0_DP_ERROR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_DDRPHY_PC_DLL_CAL_STATUS_P0_DP_ERROR , 49 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_DP_ERROR ); -REG64_FLD( MCA_DDRPHY_PC_DP16_DLL_CAL_STATUS_P0_DP_ERROR_FINE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_DDRPHY_PC_DLL_CAL_STATUS_P0_DP_ERROR_FINE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_DP_ERROR_FINE ); +REG64_FLD( MCA_DDRPHY_PC_DLL_CAL_STATUS_P0_ADR_GOOD , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR_GOOD ); +REG64_FLD( MCA_DDRPHY_PC_DLL_CAL_STATUS_P0_ADR_ERROR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR_ERROR ); +REG64_FLD( MCA_DDRPHY_PC_DLL_CAL_STATUS_P0_ADR_ERROR_FINE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADR_ERROR_FINE ); REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_RC_MASK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RC_MASK ); @@ -16957,24 +18206,28 @@ REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL , 49 , SH_UN SH_FLD_DLL ); REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL_CLOCK_GATE , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DLL_CLOCK_GATE ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_OUTPUT_STAB , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_ANALOG_OUTPUT_STAB ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB1 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_ANALOG_INPUT_STAB1 ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_SYSCLK_CLK_GATE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_SYSCLK_CLK_GATE ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DQS , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DQS ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_VPROTH , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VPROTH ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_KPRIME , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_KPRIME ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_PORTPOWERDOWN , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PORTPOWERDOWN ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ANALOG_INPUT_STAB ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ZCAL , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ZCAL ); REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DELAY_LINE_CTL_OVERRIDE , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DELAY_LINE_CTL_OVERRIDE ); REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_WR_FIFO_STAB , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_WR_FIFO_STAB ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DP16_RX_PD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DP16_RX_PD ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DP16_RX_PD_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DP16_RX_PD_LEN ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_TX_TRISTATE_CNTL , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_TX_TRISTATE_CNTL ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_VCC_REG_PD , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_VCC_REG_PD ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_RX , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RX ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_TX_TRISTATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_TX_TRISTATE ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_VREG_S , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_VREG_S ); REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_TER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADDR_MIRROR_RP0_TER ); @@ -17225,6 +18478,24 @@ REG64_FLD( MCA_DDRPHY_RC_ERROR_MASK0_P0_RD_CNTL_MASK , 48 , SH_UN REG64_FLD( MCA_DDRPHY_RC_ERROR_STATUS0_P0_RD_CNTL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RD_CNTL ); +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_GUESS_WAIT_TIME , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_GUESS_WAIT_TIME ); +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_GUESS_WAIT_TIME_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_GUESS_WAIT_TIME_LEN ); + +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CMD_PRECEDE_TIME ); +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CMD_PRECEDE_TIME_LEN ); +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_PAGE , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MPR_PAGE ); +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_PAGE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MPR_PAGE_LEN ); +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CALIBRATION_ENABLE ); +REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_SKIP_RDCENTERING ); + REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_MPR_PATTERN_BIT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MPR_PATTERN_BIT ); REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_TWO_CYCLE_ADDR_EN , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -17344,9 +18615,9 @@ REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES , 56 , SH_UN REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_TMRSC_CYCLES_LEN ); -REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P0_DEF_VALUES , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DEF_VALUES ); -REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CFG_P0_DEF_VALUES_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DEF_VALUES_LEN ); REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -17533,8 +18804,6 @@ REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_DD2_FIX_DIS , 62 , SH_UN REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_EN_RESET_WR_DELAY_WL ); -REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_DDR4_MRS_CMD_DQ_EN , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR4_MRS_CMD_DQ_EN ); REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MRS_CMD_DQ_ON ); REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -17550,6 +18819,39 @@ REG64_FLD( MCA_DDRPHY_WC_ERROR_MASK0_P0_WR_CNTL_MASK , 48 , SH_UN REG64_FLD( MCA_DDRPHY_WC_ERROR_STATUS0_P0_WR_CNTL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WR_CNTL ); +REG64_FLD( MCA_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_LOCAL_TRACE_RUN_IN ); +REG64_FLD( MCA_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT_LEN ); +REG64_FLD( MCA_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRACE_FREEZE ); +REG64_FLD( MCA_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT_LEN ); +REG64_FLD( MCA_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT_LEN ); +REG64_FLD( MCA_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION0_LT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION1_LT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_3_EVENT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_TIMEOUT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_5_EVENT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_TIMEOUT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT ); +REG64_FLD( MCA_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT_LEN ); + REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DELAYG ); REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -19573,6 +20875,13 @@ REG64_FLD( MCA_EICR_MISC , 48 , SH_UN REG64_FLD( MCA_EICR_MISC_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MISC_LEN ); +REG64_FLD( MCA_ELPR_LOG_FULL , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LOG_FULL ); +REG64_FLD( MCA_ELPR_LOG_POINTER , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LOG_POINTER ); +REG64_FLD( MCA_ELPR_LOG_POINTER_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LOG_POINTER_LEN ); + REG64_FLD( MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7 , 0 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, SH_FLD_MAINLINE_MPE_RANK_0_TO_7 ); REG64_FLD( MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM1_AND, @@ -20011,8 +21320,8 @@ REG64_FLD( MCA_MBACALFIRQ_ASYNC_IF_ERROR , 11 , SH_UN SH_FLD_ASYNC_IF_ERROR ); REG64_FLD( MCA_MBACALFIRQ_CMD_PARITY_ERROR , 12 , SH_UNT_MCA , SH_ACS_SCOM2_OR , SH_FLD_CMD_PARITY_ERROR ); -REG64_FLD( MCA_MBACALFIRQ_RESERVED_13 , 13 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED_13 ); +REG64_FLD( MCA_MBACALFIRQ_PORT_FAIL , 13 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_PORT_FAIL ); REG64_FLD( MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR , 14 , SH_UNT_MCA , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR ); REG64_FLD( MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY , 15 , SH_UNT_MCA , SH_ACS_SCOM2_OR , @@ -20301,8 +21610,8 @@ REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_ENABLE , 49 , SH_UN SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE ); REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_SINGLE_RANK , 50 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_CAL_TMR0_SINGLE_RANK ); -REG64_FLD( MCA_MBA_CAL0Q_INJECT_CAL0_PAR_ERROR , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_INJECT_CAL0_PAR_ERROR ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_51 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_51 ); REG64_FLD( MCA_MBA_CAL0Q_INJECT_1HOT_SM_ERROR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_INJECT_1HOT_SM_ERROR ); REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -20313,10 +21622,16 @@ REG64_FLD( MCA_MBA_CAL0Q_DBG_BUS_BIT , 56 , SH_UN SH_FLD_DBG_BUS_BIT ); REG64_FLD( MCA_MBA_CAL0Q_RESET_RECOVER , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RESET_RECOVER ); -REG64_FLD( MCA_MBA_CAL0Q_RESERVED_58_63 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_58_63 ); -REG64_FLD( MCA_MBA_CAL0Q_RESERVED_58_63_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_58_63_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_RANK_SM_STALL_DISABLE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_RANK_SM_STALL_DISABLE ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_SPEC_ATTN , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENABLE_SPEC_ATTN ); +REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_HOST_ATTN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENABLE_HOST_ATTN ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_61_63 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63 ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_61_63_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63_LEN ); REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE ); @@ -20469,6 +21784,134 @@ REG64_FLD( MCA_MBA_CAL3Q_RESERVED_61_63 , 61 , SH_UN REG64_FLD( MCA_MBA_CAL3Q_RESERVED_61_63_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61_63_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_ENABLE ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0 , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL0 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL0_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1 , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL1 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL1_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2 , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL2 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL2_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3 , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL3 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL3_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4 , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL4 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL4_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5 , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL5 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL5_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6 , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL6 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL6_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7 , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL7 ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL7_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_RESERVED_25_33 , 25 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_25_33 ); +REG64_FLD( MCA_MBA_DBG0Q_RESERVED_25_33_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_25_33_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ , 34 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_RESERVED_42_47 , 42 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_42_47 ); +REG64_FLD( MCA_MBA_DBG0Q_RESERVED_42_47_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_42_47_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_RRQ_GT ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_RRQ_GT_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_WRQ_GT ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_WRQ_GT_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_REF_GT ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_REF_GT_LEN ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_CAL_GT ); +REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FARB_CAL_GT_LEN ); + +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FP_DIS , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FP_DIS ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FP_DIS_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_FP_DIS_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_DIS_RD_PG ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_DIS_RD_PG_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_DIS_WR_PG ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_DIS_WR_PG_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PUP_ALL ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_PUP_ALL_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXIT_STR ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EXIT_STR_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_HP , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_REF_HP ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_HP_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_REF_HP_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_REF_SYNC ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_REF_SYNC_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_REF_SAFE ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_REF_SAFE_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CAL_SYNC ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_CAL_SYNC_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT , 44 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_RRQ_MNT_GT ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_RRQ_MNT_GT_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_WRQ_MNT_GT ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_WRQ_MNT_GT_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_SET_FIR , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_SET_FIR ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_SET_FIR_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_SET_FIR_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EMER_TH , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EMER_TH ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EMER_TH_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_EMER_TH_LEN ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_START_RECOVERY ); +REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_WAT_START_RECOVERY_LEN ); + REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_START_DLY , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_RODT_START_DLY ); REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_START_DLY_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -20607,18 +22050,18 @@ REG64_FLD( MCA_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY , 54 , SH_UN SH_FLD_CFG_DISABLE_RCD_RECOVERY ); REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALWAYS_ON , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_OE_ALWAYS_ON ); -REG64_FLD( MCA_MBA_FARB0Q_RESERVED_56 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_56 ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_FARB_CLOSE_ALL_PAGES ); REG64_FLD( MCA_MBA_FARB0Q_CFG_DISABLE_REFRESH_DURING_NOISE_WDW , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_DISABLE_REFRESH_DURING_NOISE_WDW ); REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALL_CKE_POWERED_DOWN , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN ); REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT ); -REG64_FLD( MCA_MBA_FARB0Q_CFG_IGNORE_RCD_PARITY_ERR , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_CFG_IGNORE_RCD_PARITY_ERR ); -REG64_FLD( MCA_MBA_FARB0Q_CFG_ENABLE_RCD_RW_RETRY , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_CFG_ENABLE_RCD_RW_RETRY ); +REG64_FLD( MCA_MBA_FARB0Q_RESERVED_60_61 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_61 ); +REG64_FLD( MCA_MBA_FARB0Q_RESERVED_60_61_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_60_61_LEN ); REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_OPT_RD_SIZE ); REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -20843,40 +22286,40 @@ REG64_FLD( MCA_MBA_FARB5Q_RESERVED_56_63 , 9 , SH_UN REG64_FLD( MCA_MBA_FARB5Q_RESERVED_56_63_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_63_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_RESERVED_0_1 , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_0_1 , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RESERVED_0_1 ); -REG64_FLD( MCA_MBA_FARB6Q_RESERVED_0_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_0_1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RESERVED_0_1_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_BW_SNAPSHOT ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_BW_SNAPSHOT_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_CKE_PUP_STATE ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_CKE_PUP_STATE_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_STR_STATE , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_STR_STATE , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_STR_STATE ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH , 17 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_RRQ_DEPTH ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_RRQ_DEPTH_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH , 22 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_WRQ_DEPTH ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_WRQ_DEPTH_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_RESERVED_28_31 , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_28_31 , 28 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RESERVED_28_31 ); -REG64_FLD( MCA_MBA_FARB6Q_RESERVED_28_31_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB6Q_RESERVED_28_31_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RESERVED_28_31_LEN ); -REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP , 0 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_EMER_THROTTLE_IP ); -REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE , 1 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_SAFE_REFRESH_MODE ); -REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP_CLR , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP_CLR , 2 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_EMER_THROTTLE_IP_CLR ); -REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE_CLR , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB7Q_SAFE_REFRESH_MODE_CLR , 3 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_SAFE_REFRESH_MODE_CLR ); REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_FIR_CCS_ERR_HOLD_OUT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , @@ -20903,10 +22346,8 @@ REG64_FLD( MCBIST_MBA_MCBERRPTQ_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT , 10 , SH_UN SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT ); REG64_FLD( MCBIST_MBA_MCBERRPTQ_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT ); -REG64_FLD( MCBIST_MBA_MCBERRPTQ_RESERVED_12_31 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_12_31 ); -REG64_FLD( MCBIST_MBA_MCBERRPTQ_RESERVED_12_31_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_12_31_LEN ); +REG64_FLD( MCBIST_MBA_MCBERRPTQ_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT ); REG64_FLD( MCA_MBA_PMU0Q_READ_COUNT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_READ_COUNT ); @@ -20962,30 +22403,150 @@ REG64_FLD( MCA_MBA_PMU5Q_HIGH_IDLE_COUNT , 32 , SH_UN REG64_FLD( MCA_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_HIGH_IDLE_COUNT_LEN ); -REG64_FLD( MCA_MBA_PMU6Q_TOTAL_GAP_COUNTS , 0 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_TOTAL_GAP_COUNTS ); -REG64_FLD( MCA_MBA_PMU6Q_TOTAL_GAP_COUNTS_LEN , 18 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_TOTAL_GAP_COUNTS_LEN ); -REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_COUNT , 18 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_SPECIFIC_GAP_COUNT ); -REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_COUNT_LEN , 18 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_SPECIFIC_GAP_COUNT_LEN ); -REG64_FLD( MCA_MBA_PMU6Q_GAP_LENGTH_ADDER , 36 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_GAP_LENGTH_ADDER ); -REG64_FLD( MCA_MBA_PMU6Q_GAP_LENGTH_ADDER_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_GAP_LENGTH_ADDER_LEN ); -REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_CONDITION , 39 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_SPECIFIC_GAP_CONDITION ); -REG64_FLD( MCA_MBA_PMU6Q_SPECIFIC_GAP_CONDITION_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_SPECIFIC_GAP_CONDITION_LEN ); -REG64_FLD( MCA_MBA_PMU6Q_CMD_TO_CMD_COUNT , 43 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_CMD_TO_CMD_COUNT ); -REG64_FLD( MCA_MBA_PMU6Q_CMD_TO_CMD_COUNT_LEN , 18 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_CMD_TO_CMD_COUNT_LEN ); -REG64_FLD( MCA_MBA_PMU6Q_COMMAND_PATTERN_TO_COUNT , 61 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_COMMAND_PATTERN_TO_COUNT ); -REG64_FLD( MCA_MBA_PMU6Q_COMMAND_PATTERN_TO_COUNT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_COMMAND_PATTERN_TO_COUNT_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT0_COUNTER , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT0_COUNTER ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT0_COUNTER_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT0_COUNTER_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT1_COUNTER , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT1_COUNTER ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT1_COUNTER_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT1_COUNTER_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT2_COUNTER , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT2_COUNTER ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT2_COUNTER_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT2_COUNTER_LEN ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT3_COUNTER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT3_COUNTER ); +REG64_FLD( MCA_MBA_PMU6Q_EVENT3_COUNTER_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_EVENT3_COUNTER_LEN ); + +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT0_SELECT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT0_SELECT ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT0_SELECT_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT0_SELECT_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT1_SELECT , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT1_SELECT ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT1_SELECT_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT1_SELECT_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT2_SELECT , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT2_SELECT ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT2_SELECT_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT2_SELECT_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT3_SELECT , 18 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT3_SELECT ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT3_SELECT_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_EVENT3_SELECT_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C0 , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C0 ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C0_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C0_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C1 , 26 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C1 ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C1_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C1_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C2 , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C2 ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C2_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C2_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C3 , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C3 ); +REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C3_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRESCALER_C3_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_CASCADE , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CASCADE ); +REG64_FLD( MCA_MBA_PMU7Q_CASCADE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CASCADE_LEN ); +REG64_FLD( MCA_MBA_PMU7Q_FREEZE , 35 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_FREEZE ); + +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_TYPE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_TYPE ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_TYPE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_TYPE_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_MRANK_MATCH_EN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_MRANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_SRANK_MATCH_EN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_SRANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BG_MATCH_EN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_BG_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BANK_MATCH_EN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_BANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_MRANK , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_MRANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_MRANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_MRANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_SRANK , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_SRANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_SRANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_SRANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BG , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_BG ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BG_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_BG_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BANK , 14 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_BANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD0_BANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_TYPE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_TYPE ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_TYPE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_TYPE_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_MRANK_MATCH_EN , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_MRANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_SRANK_MATCH_EN , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_SRANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BG_MATCH_EN , 21 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_BG_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BANK_MATCH_EN , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_BANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_MRANK , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_MRANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_MRANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_MRANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_SRANK , 26 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_SRANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_SRANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_SRANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BG , 29 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_BG ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BG_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_BG_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BANK , 31 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_BANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD1_BANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_TYPE , 34 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_TYPE ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_TYPE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_TYPE_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_MRANK_MATCH_EN , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_MRANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_SRANK_MATCH_EN , 37 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_SRANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BG_MATCH_EN , 38 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_BG_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BANK_MATCH_EN , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_BANK_MATCH_EN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_MRANK , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_MRANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_MRANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_MRANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_SRANK , 43 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_SRANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_SRANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_SRANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BG , 46 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_BG ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BG_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_BG_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BANK , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_BANK ); +REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_CMD2_BANK_LEN ); +REG64_FLD( MCA_MBA_PMU8Q_RESERVED_51_63 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_51_63 ); +REG64_FLD( MCA_MBA_PMU8Q_RESERVED_51_63_LEN , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_51_63_LEN ); REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_RRQ_SKIP_LIMIT ); @@ -21146,13 +22707,9 @@ REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS , 20 , SH_UN SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS ); REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN ); -REG64_FLD( MCA_MBA_TMR2Q_CFG_AUTOPC_THRESHOLD , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_CFG_AUTOPC_THRESHOLD ); -REG64_FLD( MCA_MBA_TMR2Q_CFG_AUTOPC_THRESHOLD_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_CFG_AUTOPC_THRESHOLD_LEN ); -REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63 , 35 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63 , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_63 ); -REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63_LEN , 29 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_63_LEN ); REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -21189,10 +22746,10 @@ REG64_FLD( MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD , 45 , SH_UN SH_FLD_CFG_RQ_HANG_THRESHOLD ); REG64_FLD( MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN ); -REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_53 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_53 ); -REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_FRC_ST_RD_HIT_WR , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_CFG_WRQ_FRC_ST_RD_HIT_WR ); +REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_53_54 , 53 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_53_54 ); +REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_53_54_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_53_54_LEN ); REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING ); REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -21464,10 +23021,10 @@ REG64_FLD( MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS , 1 , SH_UN SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS ); REG64_FLD( MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN ); -REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_63 , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVE_5_63 ); -REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_63_LEN , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVE_5_63_LEN ); +REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_15 , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVE_5_15 ); +REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_15_LEN , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVE_5_15_LEN ); REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_MCE_SYMBOL0_COUNT ); @@ -22136,10 +23693,12 @@ REG64_FLD( MCBIST_MCBCFGQ_RESET_KEEPER , 10 , SH_UN SH_FLD_RESET_KEEPER ); REG64_FLD( MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS ); -REG64_FLD( MCBIST_MCBCFGQ_RESERVED_12_34 , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_12_34 ); -REG64_FLD( MCBIST_MCBCFGQ_RESERVED_12_34_LEN , 23 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_12_34_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CCS_RETRY_DIS ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_34 , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_13_34 ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_34_LEN , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_13_34_LEN ); REG64_FLD( MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK , 35 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_RESET_CNTS_START_OF_RANK ); REG64_FLD( MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -22170,10 +23729,10 @@ REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR , 60 , SH_UN SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR ); REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST ); -REG64_FLD( MCBIST_MCBCFGQ_RESERVED_62 , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_62 ); -REG64_FLD( MCBIST_MCBCFGQ_RESERVED_63 , 63 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_63 ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_ENABLE_SPEC_ATTN , 62 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENABLE_SPEC_ATTN ); +REG64_FLD( MCBIST_MCBCFGQ_CFG_ENABLE_HOST_ATTN , 63 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_ENABLE_HOST_ATTN ); REG64_FLD( MCA_MCBCM_MCBIST_HALF_COMPARE_MASK , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MCBIST_HALF_COMPARE_MASK ); @@ -22307,128 +23866,20 @@ REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED8 , 56 , SH_UN REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_FIXED_SEED8_LEN ); -REG64_FLD( MCBIST_MCBISTFIRACT0_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INVALID_MAINT_ADDRESS ); -REG64_FLD( MCBIST_MCBISTFIRACT0_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_COMMAND_ADDRESS_TIMEOUT ); -REG64_FLD( MCBIST_MCBISTFIRACT0_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INTERNAL_FSM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); -REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_DATA_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRACT0_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_HARD_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT0_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_SOFT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT0_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT0_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT0_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_ICE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_PROGRAM_COMPLETE ); -REG64_FLD( MCBIST_MCBISTFIRACT0_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_CCS_SUBTEST_DONE ); -REG64_FLD( MCBIST_MCBISTFIRACT0_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_WAT_DEBUG_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT0_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_SCOM_RECOVERABLE_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRACT0_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_SCOM_FATAL_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRACT0_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_15 ); -REG64_FLD( MCBIST_MCBISTFIRACT0_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_16 ); -REG64_FLD( MCBIST_MCBISTFIRACT0_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_17 ); -REG64_FLD( MCBIST_MCBISTFIRACT0_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRACT0_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); +REG64_FLD( MCBIST_MCBISTFIRACT0_FIR_ACTION0 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION0 ); +REG64_FLD( MCBIST_MCBISTFIRACT0_FIR_ACTION0_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION0_LEN ); -REG64_FLD( MCBIST_MCBISTFIRACT1_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INVALID_MAINT_ADDRESS ); -REG64_FLD( MCBIST_MCBISTFIRACT1_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_COMMAND_ADDRESS_TIMEOUT ); -REG64_FLD( MCBIST_MCBISTFIRACT1_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INTERNAL_FSM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); -REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_DATA_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRACT1_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_HARD_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT1_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_SOFT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT1_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT1_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT1_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_ICE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_PROGRAM_COMPLETE ); -REG64_FLD( MCBIST_MCBISTFIRACT1_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_MCBIST_CCS_SUBTEST_DONE ); -REG64_FLD( MCBIST_MCBISTFIRACT1_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_WAT_DEBUG_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRACT1_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_SCOM_RECOVERABLE_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRACT1_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_SCOM_FATAL_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRACT1_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_15 ); -REG64_FLD( MCBIST_MCBISTFIRACT1_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_16 ); -REG64_FLD( MCBIST_MCBISTFIRACT1_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_17 ); -REG64_FLD( MCBIST_MCBISTFIRACT1_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRACT1_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); +REG64_FLD( MCBIST_MCBISTFIRACT1_FIR_ACTION1 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION1 ); +REG64_FLD( MCBIST_MCBISTFIRACT1_FIR_ACTION1_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION1_LEN ); -REG64_FLD( MCBIST_MCBISTFIRMASK_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_INVALID_MAINT_ADDRESS ); -REG64_FLD( MCBIST_MCBISTFIRMASK_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_COMMAND_ADDRESS_TIMEOUT ); -REG64_FLD( MCBIST_MCBISTFIRMASK_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_FSM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); -REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_MCBIST_DATA_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRMASK_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_HARD_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRMASK_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_SOFT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRMASK_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_INT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRMASK_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_RCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRMASK_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_ICE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_MCBIST_PROGRAM_COMPLETE ); -REG64_FLD( MCBIST_MCBISTFIRMASK_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_MCBIST_CCS_SUBTEST_DONE ); -REG64_FLD( MCBIST_MCBISTFIRMASK_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_WAT_DEBUG_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRMASK_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_SCOM_RECOVERABLE_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRMASK_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_SCOM_FATAL_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRMASK_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED_15 ); -REG64_FLD( MCBIST_MCBISTFIRMASK_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED_16 ); -REG64_FLD( MCBIST_MCBISTFIRMASK_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED_17 ); -REG64_FLD( MCBIST_MCBISTFIRMASK_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRMASK_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); +REG64_FLD( MCBIST_MCBISTFIRMASK_FIR_MASK , 0 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_FIR_MASK ); +REG64_FLD( MCBIST_MCBISTFIRMASK_FIR_MASK_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_FIR_MASK_LEN ); REG64_FLD( MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , SH_FLD_INVALID_MAINT_ADDRESS ); @@ -22460,8 +23911,8 @@ REG64_FLD( MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE , 13 , SH_UN SH_FLD_SCOM_RECOVERABLE_REG_PE ); REG64_FLD( MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FATAL_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED_15 ); +REG64_FLD( MCBIST_MCBISTFIRQ_WAT_DEBUG_REG_PE , 15 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , + SH_FLD_WAT_DEBUG_REG_PE ); REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_16 ); REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , @@ -22471,46 +23922,10 @@ REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR , 18 , SH_UN REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); -REG64_FLD( MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , +REG64_FLD( MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_WCLRREG, SH_FLD_INVALID_MAINT_ADDRESS ); -REG64_FLD( MCBIST_MCBISTFIRWOF_COMMAND_ADDRESS_TIMEOUT , 1 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_COMMAND_ADDRESS_TIMEOUT ); -REG64_FLD( MCBIST_MCBISTFIRWOF_INTERNAL_FSM_ERROR , 2 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_INTERNAL_FSM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_BRODCAST_OUT_OF_SYNC , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC ); -REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_DATA_ERROR , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_MCBIST_DATA_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRWOF_HARD_NCE_ETE_ATTN , 5 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_HARD_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRWOF_SOFT_NCE_ETE_ATTN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_SOFT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRWOF_INT_NCE_ETE_ATTN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_INT_NCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRWOF_RCE_ETE_ATTN , 8 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_RCE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRWOF_ICE_ETE_ATTN , 9 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_ICE_ETE_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_PROGRAM_COMPLETE , 10 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_MCBIST_PROGRAM_COMPLETE ); -REG64_FLD( MCBIST_MCBISTFIRWOF_MCBIST_CCS_SUBTEST_DONE , 11 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_MCBIST_CCS_SUBTEST_DONE ); -REG64_FLD( MCBIST_MCBISTFIRWOF_WAT_DEBUG_ATTN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_WAT_DEBUG_ATTN ); -REG64_FLD( MCBIST_MCBISTFIRWOF_SCOM_RECOVERABLE_REG_PE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_SCOM_RECOVERABLE_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRWOF_SCOM_FATAL_REG_PE , 14 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_SCOM_FATAL_REG_PE ); -REG64_FLD( MCBIST_MCBISTFIRWOF_RESERVED_15 , 15 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_15 ); -REG64_FLD( MCBIST_MCBISTFIRWOF_RESERVED_16 , 16 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_16 ); -REG64_FLD( MCBIST_MCBISTFIRWOF_RESERVED_17 , 17 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_17 ); -REG64_FLD( MCBIST_MCBISTFIRWOF_INTERNAL_SCOM_ERROR , 18 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( MCBIST_MCBISTFIRWOF_INTERNAL_SCOM_ERROR_CLONE , 19 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); +REG64_FLD( MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS_LEN , 20 , SH_UNT_MCBIST , SH_ACS_SCOM_WCLRREG, + SH_FLD_INVALID_MAINT_ADDRESS_LEN ); REG64_FLD( MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0 , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_LFSR_MASK_A0 ); @@ -23390,10 +24805,12 @@ REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDCMD_WGT , 50 , SH_UN SH_FLD_CFG_RANDCMD_WGT ); REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN , 3 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_RANDCMD_WGT_LEN ); -REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_59 , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_53_59 ); -REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_59_LEN , 7 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_53_59_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_58 , 53 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_53_58 ); +REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_58_LEN , 6 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_53_58_LEN ); +REG64_FLD( MCBIST_MCBPARMQ_CFG_CLOCK_MONITOR_EN , 59 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_CLOCK_MONITOR_EN ); REG64_FLD( MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP , 60 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_EN_RANDCMD_GAP ); REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDGAP_WGT , 61 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -23487,10 +24904,12 @@ REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 , 24 , SH_UN SH_FLD_BUSY_COUNTER_THRESHOLD2 ); REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN ); -REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD3 , 34 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_BUSY_COUNTER_THRESHOLD3 ); -REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD3_LEN , 10 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_BUSY_COUNTER_THRESHOLD3_LEN ); +REG64_FLD( MCS_PORT02_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY , 34 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_AGGRESSIVE_BUSY ); +REG64_FLD( MCS_PORT02_MCBUSYQ_RSVD_35_43 , 35 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RSVD_35_43 ); +REG64_FLD( MCS_PORT02_MCBUSYQ_RSVD_35_43_LEN , 9 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RSVD_35_43_LEN ); REG64_FLD( MCS_PORT13_MCBUSYQ_ENABLE_BUSY_COUNTERS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_ENABLE_BUSY_COUNTERS ); @@ -23510,10 +24929,12 @@ REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 , 24 , SH_UN SH_FLD_BUSY_COUNTER_THRESHOLD2 ); REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN , 10 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN ); -REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD3 , 34 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_BUSY_COUNTER_THRESHOLD3 ); -REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD3_LEN , 10 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_BUSY_COUNTER_THRESHOLD3_LEN ); +REG64_FLD( MCS_PORT13_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY , 34 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ENABLE_AGGRESSIVE_BUSY ); +REG64_FLD( MCS_PORT13_MCBUSYQ_RSVD_35_43 , 35 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RSVD_35_43 ); +REG64_FLD( MCS_PORT13_MCBUSYQ_RSVD_35_43_LEN , 9 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RSVD_35_43_LEN ); REG64_FLD( MCBIST_MCB_CNTLQ_START , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_START ); @@ -23600,10 +25021,10 @@ REG64_FLD( MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS , 0 , SH_UN REG64_FLD( MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS_LEN , 64 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , SH_FLD_EVENT_BUS_SELECTS_LEN ); -REG64_FLD( MCS_PORT13_MCEBUSEN1_MCEBUSEN0_EVENT_BUS_SELECTS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , - SH_FLD_MCEBUSEN0_EVENT_BUS_SELECTS ); -REG64_FLD( MCS_PORT13_MCEBUSEN1_MCEBUSEN0_EVENT_BUS_SELECTS_LEN , 64 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , - SH_FLD_MCEBUSEN0_EVENT_BUS_SELECTS_LEN ); +REG64_FLD( MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_SELECTS ); +REG64_FLD( MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS_LEN , 64 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EVENT_BUS_SELECTS_LEN ); REG64_FLD( MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , SH_FLD_EVENT_BUS_SELECTS ); @@ -23835,24 +25256,24 @@ REG64_FLD( MCS_MCFIR_HA_ILLEGAL_PRODUCER_ACCESS , 7 , SH_UN SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS ); REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT , 8 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_COMMAND_LIST_TIMEOUT ); -REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC , 9 , SH_UNT_MCS , SH_ACS_SCOM2_OR , - SH_FLD_COMMAND_LIST_TIMEOUT_SPEC ); -REG64_FLD( MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR , 10 , SH_UNT_MCS , SH_ACS_SCOM2_OR , +REG64_FLD( MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR , 9 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_CHANNEL_0_TIMEOUT_ERROR ); -REG64_FLD( MCS_MCFIR_CHANNEL_1_TIMEOUT_ERROR , 11 , SH_UNT_MCS , SH_ACS_SCOM2_OR , +REG64_FLD( MCS_MCFIR_CHANNEL_1_TIMEOUT_ERROR , 10 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_CHANNEL_1_TIMEOUT_ERROR ); -REG64_FLD( MCS_MCFIR_RESERVED12 , 12 , SH_UNT_MCS , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED12 ); -REG64_FLD( MCS_MCFIR_RESERVED13 , 13 , SH_UNT_MCS , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED13 ); -REG64_FLD( MCS_MCFIR_MCS_WAT , 14 , SH_UNT_MCS , SH_ACS_SCOM2_OR , - SH_FLD_MCS_WAT ); +REG64_FLD( MCS_MCFIR_MCS_WAT0 , 11 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MCS_WAT0 ); +REG64_FLD( MCS_MCFIR_MCS_WAT1 , 12 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MCS_WAT1 ); +REG64_FLD( MCS_MCFIR_MCS_WAT2 , 13 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MCS_WAT2 ); +REG64_FLD( MCS_MCFIR_MCS_WAT3 , 14 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MCS_WAT3 ); REG64_FLD( MCS_MCFIR_MIRROR_ACTION_OCCURRED , 15 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_MIRROR_ACTION_OCCURRED ); REG64_FLD( MCS_MCFIR_CENTAUR_SYNC_COMMAND_DETECTED , 16 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED ); -REG64_FLD( MCS_MCFIR_RESERVED17 , 17 , SH_UNT_MCS , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED17 ); +REG64_FLD( MCS_MCFIR_MS_WAT_DEBUG_CONFIG_REG_ERROR , 17 , SH_UNT_MCS , SH_ACS_SCOM2_OR , + SH_FLD_MS_WAT_DEBUG_CONFIG_REG_ERROR ); REG64_FLD( MCS_MCFIR_RESERVED18 , 18 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_RESERVED18 ); REG64_FLD( MCS_MCFIR_RESERVED19 , 19 , SH_UNT_MCS , SH_ACS_SCOM2_OR , @@ -23934,10 +25355,10 @@ REG64_FLD( MCS_MCMODE0_SYNC_FENCE , 15 , SH_UN SH_FLD_SYNC_FENCE ); REG64_FLD( MCS_MCMODE0_ECRESP_HASH_MODE , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_ECRESP_HASH_MODE ); -REG64_FLD( MCS_MCMODE0_ENABLE_FIR_SPEC_ATTN , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_FIR_SPEC_ATTN ); -REG64_FLD( MCS_MCMODE0_ENABLE_FIR_HOST_ATTN , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_FIR_HOST_ATTN ); +REG64_FLD( MCS_MCMODE0_RESERVED17 , 17 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED17 ); +REG64_FLD( MCS_MCMODE0_RESERVED18 , 18 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED18 ); REG64_FLD( MCS_MCMODE0_MCS_RESET_KEEPER , 19 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_MCS_RESET_KEEPER ); REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_SYNC , 20 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -23956,8 +25377,8 @@ REG64_FLD( MCS_MCMODE0_DISABLE_CL_AO_QUEUES , 26 , SH_UN SH_FLD_DISABLE_CL_AO_QUEUES ); REG64_FLD( MCS_MCMODE0_RESERVED27 , 27 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RESERVED27 ); -REG64_FLD( MCS_MCMODE0_FORCE_NON_INBAND_CL_FULL , 28 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_FORCE_NON_INBAND_CL_FULL ); +REG64_FLD( MCS_MCMODE0_RESERVED28 , 28 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED28 ); REG64_FLD( MCS_MCMODE0_MCMODE0_64B_WR_IS_PWRT , 29 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_MCMODE0_64B_WR_IS_PWRT ); REG64_FLD( MCS_MCMODE0_CL_GLOBAL_DISABLE , 30 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -23968,24 +25389,20 @@ REG64_FLD( MCS_MCMODE0_CL_FINE_DISABLE , 40 , SH_UN SH_FLD_CL_FINE_DISABLE ); REG64_FLD( MCS_MCMODE0_CL_FINE_DISABLE_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_CL_FINE_DISABLE_LEN ); -REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_64B_READ_OPS , 47 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_CENTAURP_ENABLE_64B_READ_OPS ); -REG64_FLD( MCS_MCMODE0_ENABLE_PB_PERFMON_COMMAND , 48 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_PB_PERFMON_COMMAND ); +REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_START_COMMAND , 47 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND ); +REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_STOP_COMMAND , 48 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND ); REG64_FLD( MCS_MCMODE0_SCOM_PERFMON_START_COMMAND , 49 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_SCOM_PERFMON_START_COMMAND ); REG64_FLD( MCS_MCMODE0_SCOM_PERFMON_STOP_COMMAND , 50 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_SCOM_PERFMON_STOP_COMMAND ); REG64_FLD( MCS_MCMODE0_DISABLE_PERFMON_RESET_ON_START , 51 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_PERFMON_RESET_ON_START ); -REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_START_COMMAND , 52 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND ); -REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_STOP_COMMAND , 53 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND ); -REG64_FLD( MCS_MCMODE0_RESERVED54 , 54 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED54 ); -REG64_FLD( MCS_MCMODE0_RESERVED55 , 55 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED55 ); +REG64_FLD( MCS_MCMODE0_RESERVED52_55 , 52 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED52_55 ); +REG64_FLD( MCS_MCMODE0_RESERVED52_55_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED52_55_LEN ); REG64_FLD( MCS_MCMODE0_GENERATE_MPIPL_SEQUENCE , 56 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_GENERATE_MPIPL_SEQUENCE ); REG64_FLD( MCS_MCMODE0_RESERVED57_63 , 57 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -24027,16 +25444,14 @@ REG64_FLD( MCS_MCMODE1_DISABLE_CI_LEN , 2 , SH_UN SH_FLD_DISABLE_CI_LEN ); REG64_FLD( MCS_MCMODE1_DISABLE_COMMAND_BYPASS , 54 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_COMMAND_BYPASS ); -REG64_FLD( MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_COMMAND_BYPASS_LEN ); -REG64_FLD( MCS_MCMODE1_DISABLE_FP_COMMAND_BYPASS , 59 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCMODE1_DISABLE_FP_COMMAND_BYPASS , 61 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_FP_COMMAND_BYPASS ); -REG64_FLD( MCS_MCMODE1_DISABLE_BYPASS_IN_READ_DATAFLOW , 60 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCMODE1_DISABLE_BYPASS_IN_READ_DATAFLOW , 62 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW ); -REG64_FLD( MCS_MCMODE1_RESERVED61_63 , 61 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED61_63 ); -REG64_FLD( MCS_MCMODE1_RESERVED61_63_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED61_63_LEN ); +REG64_FLD( MCS_MCMODE1_RESERVED63 , 63 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED63 ); REG64_FLD( MCS_MCMODE2_FORCE_SFSTAT_ACTIVE , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_FORCE_SFSTAT_ACTIVE ); @@ -24062,6 +25477,10 @@ REG64_FLD( MCS_MCMODE2_COLLISION_MODES , 24 , SH_UN SH_FLD_COLLISION_MODES ); REG64_FLD( MCS_MCMODE2_COLLISION_MODES_LEN , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_COLLISION_MODES_LEN ); +REG64_FLD( MCS_MCMODE2_ENABLE_FIR_SPEC_ATTN , 40 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_FIR_SPEC_ATTN ); +REG64_FLD( MCS_MCMODE2_ENABLE_FIR_HOST_ATTN , 41 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_FIR_HOST_ATTN ); REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_VALID , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3 , SH_FLD_SLOT0_VALID ); @@ -24493,26 +25912,24 @@ REG64_FLD( MCS_MCPERF1_CP_RETRY_THRESH , 39 , SH_UN SH_FLD_CP_RETRY_THRESH ); REG64_FLD( MCS_MCPERF1_CP_RETRY_THRESH_LEN , 7 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_CP_RETRY_THRESH_LEN ); -REG64_FLD( MCS_MCPERF1_RESERVED46_48 , 46 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED46_48 ); -REG64_FLD( MCS_MCPERF1_RESERVED46_48_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED46_48_LEN ); -REG64_FLD( MCS_MCPERF1_RRQ_CAPACITY_LIMIT , 49 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCPERF1_MERGE_CAPACITY_LIMIT , 46 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_MERGE_CAPACITY_LIMIT ); +REG64_FLD( MCS_MCPERF1_MERGE_CAPACITY_LIMIT_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_MERGE_CAPACITY_LIMIT_LEN ); +REG64_FLD( MCS_MCPERF1_RRQ_CAPACITY_LIMIT , 50 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RRQ_CAPACITY_LIMIT ); REG64_FLD( MCS_MCPERF1_RRQ_CAPACITY_LIMIT_LEN , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RRQ_CAPACITY_LIMIT_LEN ); -REG64_FLD( MCS_MCPERF1_WRQ_CAPACITY_LIMIT , 54 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCPERF1_WRQ_CAPACITY_LIMIT , 55 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_WRQ_CAPACITY_LIMIT ); REG64_FLD( MCS_MCPERF1_WRQ_CAPACITY_LIMIT_LEN , 6 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_WRQ_CAPACITY_LIMIT_LEN ); -REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_CMDLIST , 60 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_CMDLIST , 61 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_ENABLE_PF_DROP_CMDLIST ); -REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_SRQ , 61 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_SRQ , 62 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_ENABLE_PF_DROP_SRQ ); -REG64_FLD( MCS_MCPERF1_ENABLE_PREFETCH_PROMOTE , 62 , SH_UNT_MCS , SH_ACS_SCOM_RW , +REG64_FLD( MCS_MCPERF1_ENABLE_PREFETCH_PROMOTE , 63 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_ENABLE_PREFETCH_PROMOTE ); -REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP , 63 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_PF_DROP ); REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE0 , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_PF_DROP_VALUE0 ); @@ -24542,10 +25959,50 @@ REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ , 17 , SH_UN SH_FLD_ENABLE_REFRESH_BLOCK_NSQ ); REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_DISP , 18 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_ENABLE_REFRESH_BLOCK_DISP ); -REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_19_31 , 19 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_19_31 ); -REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_19_31_LEN , 13 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_19_31_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_PERF_THRESH , 19 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PERF_THRESH ); +REG64_FLD( MCS_PORT02_MCPERF2_PERF_THRESH_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_PERF_THRESH_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL , 24 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NSQ_LFSR_CNTL ); +REG64_FLD( MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NSQ_LFSR_CNTL_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_SQ_LFSR_CNTL , 28 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_SQ_LFSR_CNTL ); +REG64_FLD( MCS_PORT02_MCPERF2_SQ_LFSR_CNTL_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_SQ_LFSR_CNTL_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_CMD_STALL , 32 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_CMD_STALL ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_RRQ_STALL , 33 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_RRQ_STALL ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_WRQ_STALL , 34 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_WRQ_STALL ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_MERGE_STALL , 35 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_MERGE_STALL ); +REG64_FLD( MCS_PORT02_MCPERF2_EN_64_128_PB_READ , 36 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_64_128_PB_READ ); +REG64_FLD( MCS_PORT02_MCPERF2_RCTRL_CONFIG , 37 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RCTRL_CONFIG ); +REG64_FLD( MCS_PORT02_MCPERF2_RCTRL_CONFIG_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RCTRL_CONFIG_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_ALT_M , 40 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ALT_M ); +REG64_FLD( MCS_PORT02_MCPERF2_ALT_M_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_ALT_M_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_NUM_CLEAN , 44 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CLEAN ); +REG64_FLD( MCS_PORT02_MCPERF2_NUM_CLEAN_LEN , 6 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CLEAN_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_NUM_RMW_BUF , 50 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_RMW_BUF ); +REG64_FLD( MCS_PORT02_MCPERF2_NUM_RMW_BUF_LEN , 5 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_NUM_RMW_BUF_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_55_62 , 55 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_55_62 ); +REG64_FLD( MCS_PORT02_MCPERF2_RESERVED_55_62_LEN , 8 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_55_62_LEN ); +REG64_FLD( MCS_PORT02_MCPERF2_LOAD_RSVD_VALUES , 63 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_LOAD_RSVD_VALUES ); REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE0 , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_PF_DROP_VALUE0 ); @@ -24575,10 +26032,50 @@ REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ , 17 , SH_UN SH_FLD_ENABLE_REFRESH_BLOCK_NSQ ); REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_DISP , 18 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_ENABLE_REFRESH_BLOCK_DISP ); -REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_19_31 , 19 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_19_31 ); -REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_19_31_LEN , 13 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED_19_31_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_PERF_THRESH , 19 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PERF_THRESH ); +REG64_FLD( MCS_PORT13_MCPERF2_PERF_THRESH_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_PERF_THRESH_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL , 24 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NSQ_LFSR_CNTL ); +REG64_FLD( MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NSQ_LFSR_CNTL_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_SQ_LFSR_CNTL , 28 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_SQ_LFSR_CNTL ); +REG64_FLD( MCS_PORT13_MCPERF2_SQ_LFSR_CNTL_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_SQ_LFSR_CNTL_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_CMD_STALL , 32 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_CMD_STALL ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_RRQ_STALL , 33 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_RRQ_STALL ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_WRQ_STALL , 34 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_WRQ_STALL ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_MERGE_STALL , 35 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_CHARB_MERGE_STALL ); +REG64_FLD( MCS_PORT13_MCPERF2_EN_64_128_PB_READ , 36 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_64_128_PB_READ ); +REG64_FLD( MCS_PORT13_MCPERF2_RCTRL_CONFIG , 37 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RCTRL_CONFIG ); +REG64_FLD( MCS_PORT13_MCPERF2_RCTRL_CONFIG_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RCTRL_CONFIG_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_ALT_M , 40 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ALT_M ); +REG64_FLD( MCS_PORT13_MCPERF2_ALT_M_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_ALT_M_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_NUM_CLEAN , 44 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CLEAN ); +REG64_FLD( MCS_PORT13_MCPERF2_NUM_CLEAN_LEN , 6 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_CLEAN_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_NUM_RMW_BUF , 50 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_RMW_BUF ); +REG64_FLD( MCS_PORT13_MCPERF2_NUM_RMW_BUF_LEN , 5 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_NUM_RMW_BUF_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_55_62 , 55 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_55_62 ); +REG64_FLD( MCS_PORT13_MCPERF2_RESERVED_55_62_LEN , 8 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED_55_62_LEN ); +REG64_FLD( MCS_PORT13_MCPERF2_LOAD_RSVD_VALUES , 63 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_LOAD_RSVD_VALUES ); REG64_FLD( MCS_MCSYNC_CHANNEL_SELECT , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_CHANNEL_SELECT ); @@ -24601,6 +26098,37 @@ REG64_FLD( MCS_MCSYNC_SYNC_RESERVED , 25 , SH_UN REG64_FLD( MCS_MCSYNC_SYNC_RESERVED_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_SYNC_RESERVED_LEN ); +REG64_FLD( MCS_MCTO_SELECT_PB_HANG_PULSE , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SELECT_PB_HANG_PULSE ); +REG64_FLD( MCS_MCTO_SELECT_LOCAL_HANG_PULSE , 1 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_SELECT_LOCAL_HANG_PULSE ); +REG64_FLD( MCS_MCTO_RPTHANG_SELECT , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RPTHANG_SELECT ); +REG64_FLD( MCS_MCTO_RPTHANG_SELECT_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RPTHANG_SELECT_LEN ); +REG64_FLD( MCS_MCTO_RESERVED4 , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED4 ); +REG64_FLD( MCS_MCTO_TIMEOUT_VALUE , 5 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_TIMEOUT_VALUE ); +REG64_FLD( MCS_MCTO_TIMEOUT_VALUE_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_TIMEOUT_VALUE_LEN ); +REG64_FLD( MCS_MCTO_LOCAL_HANG_COMP , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_LOCAL_HANG_COMP ); +REG64_FLD( MCS_MCTO_LOCAL_HANG_COMP_LEN , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_LOCAL_HANG_COMP_LEN ); +REG64_FLD( MCS_MCTO_COMP_MASK , 24 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_COMP_MASK ); +REG64_FLD( MCS_MCTO_COMP_MASK_LEN , 8 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_COMP_MASK_LEN ); +REG64_FLD( MCS_MCTO_ENABLE_NONMIRROR_HANG , 32 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_NONMIRROR_HANG ); +REG64_FLD( MCS_MCTO_ENABLE_MIRROR_HANG , 33 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_MIRROR_HANG ); +REG64_FLD( MCS_MCTO_ENABLE_APO_HANG , 34 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_APO_HANG ); +REG64_FLD( MCS_MCTO_ENABLE_CLIB_HANG , 35 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_CLIB_HANG ); + REG64_FLD( MCA_MSR_CHIPMARK , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CHIPMARK ); REG64_FLD( MCA_MSR_CHIPMARK_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , @@ -24610,6 +26138,139 @@ REG64_FLD( MCA_MSR_RANK , 16 , SH_UN REG64_FLD( MCA_MSR_RANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RANK_LEN ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( MCA_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( MCA_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( MCA_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( MCA_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( MCA_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_LRDIMM ); REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN , 4 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -24679,84 +26340,330 @@ REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT , 0 , SH_UN SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT ); REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_2 , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_2 ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_3 , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_3 ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_4 , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_4 ); -REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE ); -REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_UE_RETRY , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_UE_RETRY , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DISABLE_UE_RETRY ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_7_8 , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_7_8 ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_7_8_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_7_8_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_10 , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_10 ); -REG64_FLD( MCA_RECR_MBSECCQ_INT_RESET_KEEPER , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_INT_RESET_KEEPER , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_INT_RESET_KEEPER ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_12_16 , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_12_16 ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_12_16_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_12_16_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_READ_POINTER_DELAY ); REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_EXIT_OVERRIDE , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_EXIT_OVERRIDE , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_EXIT_OVERRIDE ); REG64_FLD( MCA_RECR_MBSECCQ_EXIT_OVERRIDE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_22_25 , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_22_25 ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_22_25_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_22_25_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_DATA_GENERATOR_OVERRIDE , 26 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_HWMARK_EXIT1 , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_HWMARK_EXIT1 ); +REG64_FLD( MCA_RECR_MBSECCQ_DATA_GENERATOR_OVERRIDE , 12 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE ); -REG64_FLD( MCA_RECR_MBSECCQ_DATA_GENERATOR_META_ENABLE , 27 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_DATA_GENERATOR_META_ENABLE ); -REG64_FLD( MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY , 13 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY ); REG64_FLD( MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY , 31 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY ); REG64_FLD( MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_DELAY_VALID_1X , 34 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_DELAY_VALID_1X , 19 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DELAY_VALID_1X ); -REG64_FLD( MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY , 35 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY ); REG64_FLD( MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_DELAY_NONBYPASS , 37 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_DELAY_NONBYPASS , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DELAY_NONBYPASS ); -REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_SPECIAL_ATTENTION , 38 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_SPECIAL_ATTENTION , 23 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION ); -REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_HOST_ATTENTION , 39 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_HOST_ATTENTION , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_40_47 , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_40_47 ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_40_47_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_40_47_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_USE_ADDRESS_HASH , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MPE_CONFIRM , 25 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DISABLE_MPE_CONFIRM ); +REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW , 26 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ENABLE_UE_NOISE_WINDOW ); +REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION , 27 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ENABLE_TCE_CORRECTION ); +REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE , 28 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE ); +REG64_FLD( MCA_RECR_MBSECCQ_USE_ADDRESS_HASH , 29 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_USE_ADDRESS_HASH ); -REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION , 30 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DATA_INVERSION ); REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DATA_INVERSION_LEN ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_51 , 51 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_51 ); +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39 , 33 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_33_39 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_33_39_LEN ); + +REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); REG64_FLD( MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_RUNTIME_CTR ); REG64_FLD( MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN , 37 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_RUNTIME_CTR_LEN ); +REG64_FLD( MCA_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASTERS ); +REG64_FLD( MCA_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASTERS_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( MCA_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + REG64_FLD( MCA_WBMGR_TAG_INFO_BUFFER_OVERRUN , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_BUFFER_OVERRUN ); REG64_FLD( MCA_WBMGR_TAG_INFO_OVERRUN , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -24851,6 +26758,24 @@ REG64_FLD( MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_0 , 20 , SH_UN SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 ); REG64_FLD( MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_1 , 21 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 ); +REG64_FLD( MCA_WDFDBG_DBG_SPARE , 22 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SPARE ); +REG64_FLD( MCA_WDFDBG_DBG_SPARE_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SPARE_LEN ); +REG64_FLD( MCA_WDFDBG_WAT_EVENT_ENABLE , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_EVENT_ENABLE ); +REG64_FLD( MCA_WDFDBG_WAT_SPARE1 , 33 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_SPARE1 ); +REG64_FLD( MCA_WDFDBG_WAT_SPARE1_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_SPARE1_LEN ); +REG64_FLD( MCA_WDFDBG_WAT0_EVENT_SELECT , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT0_EVENT_SELECT ); +REG64_FLD( MCA_WDFDBG_WAT0_EVENT_SELECT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT0_EVENT_SELECT_LEN ); +REG64_FLD( MCA_WDFDBG_WAT1_EVENT_SELECT , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT1_EVENT_SELECT ); +REG64_FLD( MCA_WDFDBG_WAT1_EVENT_SELECT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT1_EVENT_SELECT_LEN ); REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE ); @@ -24865,11 +26790,32 @@ REG64_FLD( MCA_WECR_MBA_WRD_MODE_RESERVED_4 , 4 , SH_UN REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN ); +REG64_FLD( MCA_WESR_SYNDROME , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_SYNDROME ); +REG64_FLD( MCA_WESR_SYNDROME_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_SYNDROME_LEN ); +REG64_FLD( MCA_WESR_WHICH_8BECK , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WHICH_8BECK ); +REG64_FLD( MCA_WESR_WHICH_8BECK_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_WHICH_8BECK_LEN ); +REG64_FLD( MCA_WESR_PAR_ERR_ONLY , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PAR_ERR_ONLY ); + REG64_FLD( MCA_WOF_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_FIR ); REG64_FLD( MCA_WOF_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, SH_FLD_FIR_LEN ); +REG64_FLD( MCA_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( MCA_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + +REG64_FLD( MCA_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( MCA_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); + REG64_FLD( MCA_WRTCFG_CFG_WRITE_MODE_ECC_CHK_DIS , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS ); REG64_FLD( MCA_WRTCFG_CFG_WRITE_MODE_ECC_COR_DIS , 1 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -24895,6 +26841,24 @@ REG64_FLD( MCA_WRTDBGMCA_SEC_WBRD_DEBUG_0_SELECT , 4 , SH_UN SH_FLD_SEC_WBRD_DEBUG_0_SELECT ); REG64_FLD( MCA_WRTDBGMCA_SEC_WBRD_DEBUG_1_SELECT , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_SEC_WBRD_DEBUG_1_SELECT ); +REG64_FLD( MCA_WRTDBGMCA_DBG_SPARE_MCA , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SPARE_MCA ); +REG64_FLD( MCA_WRTDBGMCA_DBG_SPARE_MCA_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SPARE_MCA_LEN ); +REG64_FLD( MCA_WRTDBGMCA_WAT_EVENT_ENABLE_MCA , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_EVENT_ENABLE_MCA ); +REG64_FLD( MCA_WRTDBGMCA_WAT_SPARE1_MCA , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_SPARE1_MCA ); +REG64_FLD( MCA_WRTDBGMCA_WAT_SPARE1_MCA_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_SPARE1_MCA_LEN ); +REG64_FLD( MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT0_EVENT_SELECT_MCA ); +REG64_FLD( MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT0_EVENT_SELECT_MCA_LEN ); +REG64_FLD( MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT1_EVENT_SELECT_MCA ); +REG64_FLD( MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT1_EVENT_SELECT_MCA_LEN ); REG64_FLD( MCA_WRTDBGNEST_NEST_DBG_SEL_IN , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_NEST_DBG_SEL_IN ); @@ -24906,71 +26870,89 @@ REG64_FLD( MCA_WRTDBGNEST_WBMGR_DBG_1_SELECT , 3 , SH_UN SH_FLD_WBMGR_DBG_1_SELECT ); REG64_FLD( MCA_WRTDBGNEST_WRCNTL_DBG_SELECT , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_WRCNTL_DBG_SELECT ); - -REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE , 0 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WRTDBGNEST_DBG_SPARE_NEST , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SPARE_NEST ); +REG64_FLD( MCA_WRTDBGNEST_DBG_SPARE_NEST_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DBG_SPARE_NEST_LEN ); +REG64_FLD( MCA_WRTDBGNEST_WAT_EVENT_ENABLE_NEST , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_EVENT_ENABLE_NEST ); +REG64_FLD( MCA_WRTDBGNEST_WAT_SPARE1_NEST , 17 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_SPARE1_NEST ); +REG64_FLD( MCA_WRTDBGNEST_WAT_SPARE1_NEST_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT_SPARE1_NEST_LEN ); +REG64_FLD( MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST , 20 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT0_EVENT_SELECT_NEST ); +REG64_FLD( MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT0_EVENT_SELECT_NEST_LEN ); +REG64_FLD( MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST , 24 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT1_EVENT_SELECT_NEST ); +REG64_FLD( MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_WAT1_EVENT_SELECT_NEST_LEN ); + +REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE , 0 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_ERR_TYPE ); -REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_ERR_TYPE_LEN ); -REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_SYNDROME ); -REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_SYNDROME_LEN ); -REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE , 16 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE , 16 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_ERR_TYPE ); -REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_ERR_TYPE_LEN ); -REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME , 24 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME , 24 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_SYNDROME ); -REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_SYNDROME_LEN ); -REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE , 32 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE , 32 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_ERR_TYPE ); -REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_ERR_TYPE_LEN ); -REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME , 40 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME , 40 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_SYNDROME ); -REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_SYNDROME_LEN ); -REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE , 48 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE , 48 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_ERR_TYPE ); -REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_ERR_TYPE_LEN ); -REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME , 56 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME , 56 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_SYNDROME ); -REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_RW , +REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME_LEN , 8 , SH_UNT_MCA_WDF , SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_SYNDROME_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE , 0 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE , 0 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_ERR_TYPE ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_ERR_TYPE_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_SYNDROME ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW0_SYNDROME_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE , 16 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE , 16 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_ERR_TYPE ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_ERR_TYPE_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME , 24 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME , 24 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_SYNDROME ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW1_SYNDROME_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE , 32 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE , 32 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_ERR_TYPE ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_ERR_TYPE_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME , 40 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME , 40 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_SYNDROME ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW2_SYNDROME_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE , 48 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE , 48 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_ERR_TYPE ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE_LEN , 3 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_ERR_TYPE_LEN ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME , 56 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME , 56 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_SYNDROME ); -REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW , +REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME_LEN , 8 , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART, SH_FLD_DW3_SYNDROME_LEN ); #endif |
