Adds hardware specific definitions to initfiles

Change-Id: I140350f9de185b18de3a3f39284f98a09e5e07f4
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77695
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78022
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
index a81664989..47f6f85fe 100644
--- a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
+++ b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
@@ -117,6 +117,7 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
         fapi2::ATTR_MEM_EFF_DRAM_CL_Type l_TGT1_ATTR_MEM_EFF_DRAM_CL;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_CL, TGT1, l_TGT1_ATTR_MEM_EFF_DRAM_CL));
         uint64_t l_def_IS_IBM_SIM = literal_0;
+        uint64_t l_def_IS_HW = (l_TGT2_ATTR_IS_SIMULATION == literal_0);
         fapi2::ATTR_MEM_DRAM_CWL_Type l_TGT1_ATTR_MEM_DRAM_CWL;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_CWL, TGT1, l_TGT1_ATTR_MEM_DRAM_CWL));
         fapi2::ATTR_MEM_EFF_FREQ_Type l_TGT1_ATTR_MEM_EFF_FREQ;
@@ -246,6 +247,11 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             {
                 l_scom_buffer.insert<36, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_4) + l_def_RDIMM_Add_latency) );
             }
+            else if (l_def_IS_HW)
+            {
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_11) + l_def_RDIMM_Add_latency) +
+                        l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK) );
+            }
 
             if (l_def_IS_MICROSEMI_SIM)
             {
@@ -255,6 +261,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             {
                 l_scom_buffer.insert<47, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_4) + l_def_RDIMM_Add_latency) );
             }
+            else if (l_def_IS_HW)
+            {
+                l_scom_buffer.insert<47, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_9) + l_def_RDIMM_Add_latency) );
+            }
 
             if (l_def_IS_MICROSEMI_SIM)
             {
@@ -264,6 +274,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             {
                 l_scom_buffer.insert<42, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_4) + l_def_RDIMM_Add_latency) );
             }
+            else if (l_def_IS_HW)
+            {
+                l_scom_buffer.insert<42, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_9) + l_def_RDIMM_Add_latency) );
+            }
 
             if (l_def_IS_MICROSEMI_SIM)
             {
@@ -273,6 +287,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             {
                 l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_9) + l_def_RDIMM_Add_latency) );
             }
+            else if (l_def_IS_HW)
+            {
+                l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_14) + l_def_RDIMM_Add_latency) );
+            }
 
             if (l_def_IS_MICROSEMI_SIM)
             {
@@ -282,6 +300,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             {
                 l_scom_buffer.insert<57, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_2) + l_def_RDIMM_Add_latency) );
             }
+            else if (l_def_IS_HW)
+            {
+                l_scom_buffer.insert<57, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_7) + l_def_RDIMM_Add_latency) );
+            }
 
             if (l_def_IS_MICROSEMI_SIM)
             {
@@ -291,6 +313,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             {
                 l_scom_buffer.insert<52, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_2) + l_def_RDIMM_Add_latency) );
             }
+            else if (l_def_IS_HW)
+            {
+                l_scom_buffer.insert<52, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_7) + l_def_RDIMM_Add_latency) );
+            }
 
             l_scom_buffer.insert<24, 6, 58, uint64_t>(literal_24 );
             l_scom_buffer.insert<0, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - l_TGT1_ATTR_MEM_DRAM_CWL) +
@@ -780,6 +806,7 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
             }
 
             l_scom_buffer.insert<46, 11, 53, uint64_t>(l_def_REFRESH_INTERVAL );
+            l_scom_buffer.insert<62, 1, 63, uint64_t>(literal_1 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x8011437ull, l_scom_buffer));
         }
         {