Update phy_pharams structure, tests, and exp attrs

Change-Id: I02ddbd9a764d55af3edd786f6b5e7799a174a914
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72070
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73248
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 48 insertions, 57 deletions

diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml
index 927bdcf83..8ff5a9df3 100644
--- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml
+++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml
@@ -120,42 +120,17 @@
         <mssAccessorName>mvpd_fwms</mssAccessorName>
     </attribute>
 
+    <!-- user_input_msdg attribute overrides start -->
     <attribute>
-        <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id>
-        <targetType>TARGET_TYPE_MEM_PORT</targetType>
-        <description>
-            Enable Special mode for Emulation Support
-        </description>
-        <valueType>uint8</valueType>
-        <initToZero></initToZero>
-        <enum>NORMAL = 0, EMULATION = 1</enum>
-        <writeable/>
-        <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName>
-    </attribute>
-
-    <attribute>
-        <id>ATTR_MEM_EXP_CHIP_SELECT</id>
+        <id>ATTR_MEM_EXP_CS_PRESENT</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
             Indicate presence of DRAM at each Chip Select for PHY
         </description>
-        <valueType>uint8</valueType>
         <initToZero></initToZero>
+        <valueType>uint16</valueType>
         <writeable/>
-        <mssAccessorName>exp_chip_select</mssAccessorName>
-    </attribute>
-
-    <attribute>
-        <id>ATTR_MEM_EXP_PHY_EQUALIZATION</id>
-        <targetType>TARGET_TYPE_MEM_PORT</targetType>
-        <description>
-           Phy Equalization mode enable
-        </description>
-        <valueType>uint8</valueType>
-        <initToZero></initToZero>
-        <enum>DISABLE = 0, ENABLE = 1</enum>
-        <writeable/>
-        <mssAccessorName>exp_phy_equalization</mssAccessorName>
+        <mssAccessorName>exp_cs_present</mssAccessorName>
     </attribute>
 
     <attribute>
@@ -183,70 +158,71 @@
     </attribute>
 
     <attribute>
-        <id>ATTR_MEM_EXP_ODT_MAP_CS_WR</id>
+        <id>ATTR_MEM_EXP_RCD_DIC</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
-           Desired ODT Value to write to the ranks
+           CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05
         </description>
-        <valueType>uint8</valueType>
+        <valueType>uint16</valueType>
         <initToZero></initToZero>
         <writeable/>
-        <mssAccessorName>exp_odt_map_cs_wr</mssAccessorName>
+        <mssAccessorName>exp_rcd_dic</mssAccessorName>
     </attribute>
 
     <attribute>
-        <id>ATTR_MEM_EXP_ODT_MAP_CS_RD</id>
+        <id>ATTR_MEM_EXP_RCD_VOLTAGE_CTRL</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
-           Desired ODT Value when reading from the ranks
+           RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x
         </description>
-        <valueType>uint8</valueType>
+        <valueType>uint16</valueType>
         <initToZero></initToZero>
         <writeable/>
-        <mssAccessorName>exp_odt_map_cs_rd</mssAccessorName>
+        <mssAccessorName>exp_rcd_voltage_ctrl</mssAccessorName>
     </attribute>
 
     <attribute>
-        <id>ATTR_MEM_EXP_RCD_DIC</id>
+        <id>ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
-           CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05
+            Ranks that have address mirroring.
+            This data is derived from SPD or VPD.
+            Note: This is a bit-wise map and muliple ranks can be mirrored.
         </description>
-        <valueType>uint8</valueType>
         <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <array>2</array>
         <writeable/>
-        <mssAccessorName>exp_rcd_dic</mssAccessorName>
+        <mssAccessorName>exp_dram_address_mirroring</mssAccessorName>
     </attribute>
 
     <attribute>
-        <id>ATTR_MEM_EXP_RCD_VOLTAGE_CTRL</id>
+        <id>ATTR_MEM_EXP_RCD_SLEW_RATE</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
-           RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x
+            RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05
         </description>
-        <valueType>uint8</valueType>
         <initToZero></initToZero>
+        <valueType>uint16</valueType>
         <writeable/>
-        <mssAccessorName>exp_rcd_voltage_ctrl</mssAccessorName>
+        <mssAccessorName>exp_rcd_slew_rate</mssAccessorName>
     </attribute>
 
     <attribute>
-        <id>ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING</id>
+        <id>ATTR_MEM_EXP_3DS_HEIGHT</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
-            Ranks that have address mirroring.
-            This data is derived from SPD or VPD.
-            Note: This is a bit-wise map and muliple ranks can be mirrored.
+            Explorer setting for 3DS stack
         </description>
         <initToZero></initToZero>
-        <valueType>uint8</valueType>
-        <array>2</array>
+        <valueType>uint16</valueType>
+        <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum>
         <writeable/>
-        <mssAccessorName>exp_dram_address_mirroring</mssAccessorName>
+        <mssAccessorName>exp_3ds_height</mssAccessorName>
     </attribute>
 
     <attribute>
-        <id>ATTR_MEM_EXP_SPD_CL</id>
+        <id>ATTR_MEM_EXP_SPD_CL_SUPPORTED</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
             Cas Latency Supported by DRAM
@@ -254,19 +230,34 @@
         <initToZero></initToZero>
         <valueType>uint32</valueType>
         <writeable/>
-        <mssAccessorName>exp_spd_cl</mssAccessorName>
+        <mssAccessorName>exp_spd_cl_supported</mssAccessorName>
     </attribute>
 
     <attribute>
-        <id>ATTR_MEM_EXP_RCD_SLEW_RATE</id>
+        <id>ATTR_MEM_EXP_SPD_TAA_MIN</id>
         <targetType>TARGET_TYPE_MEM_PORT</targetType>
         <description>
-            RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05
+          Minimum Cas Latency Time (tAAmin) in Picosecond (Byte 24)
         </description>
         <initToZero></initToZero>
         <valueType>uint16</valueType>
         <writeable/>
-        <mssAccessorName>exp_rcd_slew_rate</mssAccessorName>
+        <mssUnits>ps</mssUnits>
+        <mssAccessorName>exp_spd_taa_min</mssAccessorName>
+    </attribute>
+
+    <attribute>
+        <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id>
+        <targetType>TARGET_TYPE_MEM_PORT</targetType>
+        <description>
+            Enable Special mode for Emulation Support
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <mssUnits>bool</mssUnits>
+        <enum>NORMAL = 0, EMULATION = 1</enum>
+        <writeable/>
+        <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName>
     </attribute>
 
 </attributes>