Add PRBS training sequence to exp_omi_setup

Change-Id: I85630e3959cd95317c5026f1efaaa8062c4bbbe6
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80238
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80331
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

5 files changed, 222 insertions, 1 deletions

diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C
index 94247b21b..4beb604b6 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C
@@ -37,9 +37,11 @@
 #include <generic/memory/lib/utils/c_str.H>
 #include <lib/exp_attribute_accessors_manual.H>
 #include <lib/omi/exp_omi_utils.H>
+#include <lib/workarounds/exp_omi_workarounds.H>
 #include <lib/i2c/exp_i2c.H>
 #include <generic/memory/mss_git_data_helper.H>
 #include <generic/memory/lib/mss_generic_attribute_getters.H>
+#include <generic/memory/lib/mss_generic_system_attribute_getters.H>
 
 extern "C"
 {
@@ -59,6 +61,7 @@ extern "C"
         uint8_t l_edpl_disable = 0;
         bool l_is_enterprise = false;
         bool l_is_half_dimm = false;
+        bool l_workaround_required = false;
         std::vector<uint8_t> l_boot_config_data;
         uint8_t l_dl_layer_boot_mode = fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_DL_LAYER_BOOT_MODE_NON_DL_TRAINING;
 
@@ -98,6 +101,19 @@ extern "C"
         FAPI_TRY(mss::exp::omi::write_dlx_config1(i_target, dlx_config1_data));
         FAPI_INF("%s EDPL enable: ", mss::c_str(i_target), l_edpl_disable ? "false" : "true");
 
+        // Run the workaround if it's needed
+        FAPI_TRY(mss::exp::workarounds::omi::is_prbs_ocmb_required(i_target, l_workaround_required));
+
+        if (l_workaround_required)
+        {
+            uint8_t l_dl_x4_backoff_en = 0;
+
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE, i_target, l_dl_x4_backoff_en),
+                     "Error getting ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE");
+
+            FAPI_TRY(mss::exp::workarounds::omi::prbs_ocmb(i_target, l_dl_x4_backoff_en));
+        }
+
     fapi_try_exit:
         return fapi2::current_err;
     }
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C
index 5c5372851..aad9a91ab 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C
@@ -37,7 +37,9 @@
 #include <lib/omi/exp_omi_utils.H>
 #include <lib/shared/exp_consts.H>
 #include <lib/i2c/exp_i2c_fields.H>
+#include <generic/memory/lib/mss_generic_attribute_getters.H>
 #include <mss_explorer_attribute_getters.H>
+#include <generic/memory/lib/mss_generic_system_attribute_getters.H>
 
 namespace mss
 {
@@ -45,6 +47,42 @@ namespace exp
 {
 namespace omi
 {
+
+///
+/// @brief Set the OMI_DL0 configuration register for a given mode
+///
+/// @param[in] i_target OCMB target
+/// @param[in] i_train_mode mode to use
+/// @param[in] i_dl_x4_backoff_en backoff enable bit
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success
+/// @note Algorithm from p9a_omi_train.C
+///
+fapi2::ReturnCode setup_omi_dl0_config0(
+    const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+    const uint8_t i_train_mode,
+    const uint8_t i_dl_x4_backoff_en)
+{
+    fapi2::buffer<uint64_t> l_config0;
+
+    // Get the "reset" values so we can just overwrite with the changes
+    FAPI_TRY(fapi2::getScom(i_target, EXPLR_DLX_DL0_CONFIG0, l_config0),
+             "Error reading EXPLR_DLX_DL0_CONFIG0 on %s", mss::c_str(i_target));
+
+    // CFG_DL0_HALF_WIDTH_BACKOFF_ENABLE: dl0 x4 backoff enabled
+    l_config0.writeBit<EXPLR_DLX_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE>(i_dl_x4_backoff_en);
+
+    // CFG_DL0_TRAIN_MODE: dl0 train mode
+    l_config0.insertFromRight<EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE,
+                              EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE_LEN>(i_train_mode);
+
+    // All other bits will be left at their default values
+    FAPI_TRY( fapi2::putScom(i_target, EXPLR_DLX_DL0_CONFIG0, l_config0),
+              "Error writing EXPLR_DLX_DL0_CONFIG0 on %s", mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
 namespace train
 {
 
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H
index 3658100b1..577743a06 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H
@@ -202,6 +202,20 @@ inline fapi2::ReturnCode write_dlx_config1( const fapi2::Target<fapi2::TARGET_TY
     return fapi2::putScom(i_target, EXPLR_DLX_DL0_CONFIG1, i_data);
 }
 
+///
+/// @brief Set the OMI_DL0 configuration register for a given mode
+///
+/// @param[in] i_target OCMB target
+/// @param[in] i_train_mode mode to use
+/// @param[in] i_dl_x4_backoff_en backoff enable bit
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success
+/// @note Algorithm from p9a_omi_train.C
+///
+fapi2::ReturnCode setup_omi_dl0_config0(
+    const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+    const uint8_t i_train_mode,
+    const uint8_t i_dl_x4_backoff_en);
+
 namespace train
 {
 
@@ -213,7 +227,6 @@ namespace train
 ///
 fapi2::ReturnCode setup_fw_boot_config( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
                                         std::vector<uint8_t>& o_data );
-
 } // ns train
 
 } // ns omi
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C
index 864cd2603..8c1225f0f 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C
@@ -22,3 +22,104 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_omi_workarounds.C
+/// @brief Workarounds for exp_omi_* procedures
+///
+// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: Memory
+
+#include <generic/memory/lib/utils/find.H>
+#include <lib/workarounds/exp_omi_workarounds.H>
+#include <lib/shared/exp_consts.H>
+#include <lib/omi/exp_omi_utils.H>
+#include <generic/memory/lib/mss_generic_attribute_getters.H>
+#include <generic/memory/lib/mss_generic_system_attribute_getters.H>
+
+namespace mss
+{
+namespace exp
+{
+namespace workarounds
+{
+namespace omi
+{
+///
+/// @brief Determine if OCMB PRBS workaround needs to be performed
+///
+/// @param[in] i_ocmb_chip OCMB target
+/// @param[out] o_required workaround needs to be performed
+/// @return FAPI2_RC_SUCCESS iff success
+///
+fapi2::ReturnCode is_prbs_ocmb_required(
+    const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip,
+    bool& o_required)
+{
+    // Check chip type
+    uint8_t l_proc_type = 0;
+    const auto& l_proc_chip = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_ocmb_chip);
+    FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, l_proc_chip, l_proc_type),
+             "Error getting ATTR_NAME of %s", mss::c_str(l_proc_chip));
+
+    // OCMB Workaround Logic:
+    // Axone: OCMB workaround off
+    // Non-axone (Apollo): OCMB workaround on
+    // P10 - No workaround required (no enum for this yet, so we must revisit this when the time comes)
+    o_required = l_proc_type != fapi2::ENUM_ATTR_NAME_AXONE;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Performs OCMB PRBS workaround
+///
+/// @param[in] i_ocmb_chip OCMB chip
+/// @param[in] i_dl_x4_backoff_en backoff enable
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success
+///
+fapi2::ReturnCode prbs_ocmb(
+    const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip,
+    const uint8_t i_dl_x4_backoff_en)
+{
+    FAPI_DBG("Performing PRBS OCMB workaround on %s", mss::c_str(i_ocmb_chip));
+
+    uint8_t l_sim = 0;
+    uint32_t l_prbs_time = 0;
+    uint64_t l_prbs_time_scaled = 0;
+
+    FAPI_TRY( mss::attr::get_is_simulation( l_sim) );
+
+    FAPI_TRY(mss::attr::get_omi_dl_preipl_prbs_time(mss::find_target<fapi2::TARGET_TYPE_OMI>(i_ocmb_chip), l_prbs_time),
+             "Error from FAPI_ATTR_GET (ATTR_OMI_DL_PREIPL_PRBS_TIME)");
+    l_prbs_time_scaled = l_prbs_time * mss::common_timings::DELAY_1MS;
+
+    // State 6
+    FAPI_TRY(mss::exp::omi::setup_omi_dl0_config0(i_ocmb_chip,
+             mss::omi::train_mode::TX_TRAINING_STATE3,
+             i_dl_x4_backoff_en));
+
+    // Set configurable delay based on the PRBS ATTR and SIM mode
+    FAPI_TRY(fapi2::delay(l_prbs_time_scaled, mss::common_timings::DELAY_1US));
+    FAPI_DBG("OMI Training Pre-ipl PRBS Time = %dns",
+             (l_sim ? mss::common_timings::DELAY_1US : l_prbs_time_scaled));
+
+    // Enable training state 1 to send Pattern A
+    FAPI_TRY(mss::exp::omi::setup_omi_dl0_config0(i_ocmb_chip,
+             mss::omi::train_mode::TX_PATTERN_A,
+             i_dl_x4_backoff_en));
+
+    // Not calling with ENABLE_AUTO_TRAINING for explorer
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+} // omi
+} // workarounds
+} // exp
+} // mss
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H
index 72ffdd293..7a41c76e1 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H
@@ -22,3 +22,56 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file exp_omi_workarounds.H
+/// @brief Workarounds for exp_omi_* procedures
+///
+// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: Memory
+
+#ifndef EXP_OMI_WORKAROUNDS_H_
+#define EXP_OMI_WORKAROUNDS_H_
+
+#include <fapi2.H>
+
+namespace mss
+{
+namespace exp
+{
+namespace workarounds
+{
+namespace omi
+{
+
+///
+/// @brief Determine if OCMB PRBS workaround needs to be performed
+///
+/// @param[in] i_ocmb_chip OCMB target
+/// @param[out] o_required workaround needs to be performed
+/// @return FAPI2_RC_SUCCESS iff success
+///
+fapi2::ReturnCode is_prbs_ocmb_required(
+    const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip,
+    bool& o_required);
+
+///
+/// @brief Performs OCMB PRBS workaround
+///
+/// @param[in] i_ocmb_chip OCMB chip
+/// @param[in] i_dl_x4_backoff_en backoff enable
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success
+///
+fapi2::ReturnCode prbs_ocmb(
+    const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip,
+    const uint8_t i_dl_x4_backoff_en);
+
+} // omi
+} // workarounds
+} // exp
+} // mss
+
+#endif