diff options
| author | Louis Stermole <stermole@us.ibm.com> | 2019-06-24 10:49:10 -0400 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-06-26 10:09:44 -0500 |
| commit | 6a075926870a46819e91d64cadb6060bd237e46d (patch) | |
| tree | 298173b8b7f170ae6dcd3b608550505856ccddda /src/import/chips/ocmb/explorer/procedures/hwp/memory | |
| parent | 1dc17625bd831f23897bba41609670a80d8e94d4 (diff) | |
| download | talos-hostboot-6a075926870a46819e91d64cadb6060bd237e46d.tar.gz talos-hostboot-6a075926870a46819e91d64cadb6060bd237e46d.zip | |
Fix alignment of exp_draminit training response display
Change-Id: I16ba7826fd3af5199e8921aa090cd8748e8a0b8f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79391
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: RYAN P. KING <rpking@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79416
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/ocmb/explorer/procedures/hwp/memory')
| -rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C index 67d2a73ba..477335d6f 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C @@ -260,7 +260,7 @@ fapi2::ReturnCode display_response_timing(const fapi2::Target<fapi2::TARGET_TYPE FAPI_INF("%s DFIMRL_DDRCLK_trained: %u", mss::c_str(i_target), i_training_info.tm_resp.DFIMRL_DDRCLK_trained); // RD to RD - FAPI_DBG("%s RD-to-RD : 0 1 2 3", mss::c_str(i_target)); + FAPI_DBG("%s RD-to-RD : 0 1 2 3", mss::c_str(i_target)); for(uint8_t l_rank_n = 0; l_rank_n < l_num_rank_per_ocmb; ++l_rank_n) { @@ -270,7 +270,7 @@ fapi2::ReturnCode display_response_timing(const fapi2::Target<fapi2::TARGET_TYPE } // WR to WR - FAPI_DBG("%s WR-to-WR : 0 1 2 3", mss::c_str(i_target)); + FAPI_DBG("%s WR-to-WR : 0 1 2 3", mss::c_str(i_target)); for(uint8_t l_rank_n = 0; l_rank_n < l_num_rank_per_ocmb; ++l_rank_n) { @@ -280,7 +280,7 @@ fapi2::ReturnCode display_response_timing(const fapi2::Target<fapi2::TARGET_TYPE } // WR to RD - FAPI_DBG("%s WR-to-RD : 0 1 2 3", mss::c_str(i_target)); + FAPI_DBG("%s WR-to-RD : 0 1 2 3", mss::c_str(i_target)); for(uint8_t l_rank_n = 0; l_rank_n < l_num_rank_per_ocmb; ++l_rank_n) { @@ -290,7 +290,7 @@ fapi2::ReturnCode display_response_timing(const fapi2::Target<fapi2::TARGET_TYPE } // RD to WR - FAPI_DBG("%s RD-to-WR : 0 1 2 3", mss::c_str(i_target)); + FAPI_DBG("%s RD-to-WR : 0 1 2 3", mss::c_str(i_target)); for(uint8_t l_rank_n = 0; l_rank_n < l_num_rank_per_ocmb; ++l_rank_n) { |
