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author | Alvin Wang <wangat@tw.ibm.com> | 2019-01-29 02:13:09 -0600 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-22 15:19:01 -0600 |
commit | b377d2191c6ab8a2ddd3211f98bf21e7926e0aad (patch) | |
tree | def39aecd06a758f713902c833000eeb0d3b5669 /src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H | |
parent | 66a5ca389cf9f089e7f9067a96d5e10ffc88a6df (diff) | |
download | talos-hostboot-b377d2191c6ab8a2ddd3211f98bf21e7926e0aad.tar.gz talos-hostboot-b377d2191c6ab8a2ddd3211f98bf21e7926e0aad.zip |
Adds exp_draminit_mc
Change-Id: Ia37e054a68446fa81f6bfe120ebc4afcaa508baf
Original-Change-Id: Ib4a31d2893c5524e3b2ce9128a2c4900bd82b2c0
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68597
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72341
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H')
-rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H index e144b9c6f..50f04a936 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H @@ -22,3 +22,115 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_port.H +/// @brief Code to support ports +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef __MSS_EXP_PORT_H_ +#define __MSS_EXP_PORT_H_ + +#include <fapi2.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> +#include <lib/exp_attribute_accessors_manual.H> +#include <generic/memory/lib/utils/mc/gen_mss_port.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <mss_explorer_attribute_getters.H> + +namespace mss +{ + +/// +/// @brief ATTR_MSS_MEM_MVPD_FWMS getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Mark store records from MPVD Lx +/// keyword +/// +template<> +inline fapi2::ReturnCode mvpd_fwms<mss::mc_type::EXPLORER>(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint32_t (&o_array)[mss::MARK_STORE_COUNT]) +{ + return mss::attr::get_mvpd_fwms(i_target, o_array); +} + + +// ocmb mem port traits +/// +/// @class Traits and policy class for port code - specialization for the ocmb mem port type +/// +template<> +class portTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP> +{ + public: + // scom register definition + static constexpr uint64_t MBARPC0Q_REG = EXPLR_SRQ_MBARPC0Q; + + static constexpr uint64_t FARB0Q_REG = EXPLR_SRQ_MBA_FARB0Q; + static constexpr uint64_t FARB5Q_REG = EXPLR_SRQ_MBA_FARB5Q; + static constexpr uint64_t FARB6Q_REG = EXPLR_SRQ_MBA_FARB6Q; + static constexpr uint64_t FARB9Q_REG = EXPLR_SRQ_MBA_FARB9Q; + static constexpr uint64_t REFRESH_REG = EXPLR_SRQ_MBAREF0Q; + static constexpr uint64_t ECC_REG = EXPLR_RDF_RECR; + static constexpr uint64_t DSM0Q_REG = EXPLR_SRQ_MBA_DSM0Q; + static constexpr uint64_t FWMS_REG = EXPLR_RDF_FWMS0; + + static constexpr uint64_t RRQ_REG = EXPLR_SRQ_MBA_RRQ0Q; + static constexpr uint64_t WRQ_REG = EXPLR_SRQ_MBA_WRQ0Q; + + static constexpr uint64_t MAGIC_NUMBER_SIM = 765; + static constexpr uint64_t MAGIC_NUMBER_NOT_SIM = 196605; + + // scom register field definition + enum + { + CFG_MIN_MAX_DOMAINS_ENABLE = EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE, + CFG_CCS_INST_RESET_ENABLE = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE, + CFG_DDR_RESETN = EXPLR_SRQ_MBA_FARB5Q_CFG_DDR_RESETN, + CFG_CCS_ADDR_MUX_SEL = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL, + //TODO: It's not defined in scom register header file. Change this once it's available in scom address header file + CFG_INIT_COMPLETE = 32, //EXPLR_SRQ_MBA_FARB6Q_CFG_INIT_COMPLETE, + CFG_ZQ_PER_CAL_ENABLE = EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_ENABLE, + + REFRESH_ENABLE = EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_ENABLE, + + ECC_CHECK_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT, + ECC_CORRECT_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT, + ECC_USE_ADDR_HASH = EXPLR_RDF_RECR_MBSECCQ_USE_ADDRESS_HASH, + + PORT_FAIL_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE, + DFI_INIT_START = EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE, + RCD_RECOVERY_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY, + + RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, + RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION, + RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN, + DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY, + DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, + DSM0Q_WRDONE_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY, + DSM0Q_WRDONE_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY_LEN, + FARB0Q_RCD_PROTECTION_TIME = EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME, + FARB0Q_RCD_PROTECTION_TIME_LEN = EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN, + + FWMS0_MARK = EXPLR_RDF_FWMS0_MARK, + FWMS0_MARK_LEN = EXPLR_RDF_FWMS0_MARK_LEN, + FWMS0_EXIT_1 = EXPLR_RDF_FWMS0_EXIT_1, + + RRQ_FIFO_MODE = EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE, + WRQ_FIFO_MODE = EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE, + }; +}; + + +}// mss + +#endif |