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author | Prem Shanker Jha <premjha2@in.ibm.com> | 2018-10-26 00:44:13 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-11-05 22:09:40 -0600 |
commit | c826f6afcb57031ebf3a8fa948926feaf5792497 (patch) | |
tree | 2b995045c656108cc6a49a683eaae17d45b456cf /src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C | |
parent | 83335d59ac593a543bcbe8c9c2f030798c02a2dc (diff) | |
download | talos-hostboot-c826f6afcb57031ebf3a8fa948926feaf5792497.tar.gz talos-hostboot-c826f6afcb57031ebf3a8fa948926feaf5792497.zip |
PM: Handled SCOM failures while determining unit availability.
HWP reads a quad and core level registers to determine clock
status for cache and core respectively. If this SCOM fails, HWP
returns a generic non success RC but it doesn't initialize the
attributes appropriately. As a result, caller doesn't get an
idea on extent of availability of core and cache for operation
like SCOM or Scan. Commit addresses it by handling the RC and
initializing the attribute appropraitely.
Key_Cronus_Test=PM_REGRESS
Change-Id: Ib5e46ad11e2cf817f72a4fec20815dbca354ac51
CQ: SW449148
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68033
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68038
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C')
0 files changed, 0 insertions, 0 deletions