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| author | Mark Pizzutillo <Mark.Pizzutillo@ibm.com> | 2019-04-15 16:08:22 -0400 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-05-23 10:47:25 -0500 |
| commit | 1dab92e705f6f8c893a09ff250eab1a762f7e88f (patch) | |
| tree | 057239c62c8518640bad8c1a3ea306a84c108725 /src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml | |
| parent | 5de4c5ec41bf05f8e3d735ded4cc864d017e6279 (diff) | |
| download | talos-hostboot-1dab92e705f6f8c893a09ff250eab1a762f7e88f.tar.gz talos-hostboot-1dab92e705f6f8c893a09ff250eab1a762f7e88f.zip | |
Add PMIC enable procedure code and UTs
Change-Id: Iac5cd8016efa705be6512b842e0e793eb3d4c5fa
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74639
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77132
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml')
| -rw-r--r-- | src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml b/src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml index fea79e82c..6c2437728 100644 --- a/src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml +++ b/src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml @@ -44,4 +44,92 @@ </callout> </hwpError> + <hwpError> + <rc>RC_PMIC_CHIP_NOT_RECOGNIZED</rc> + <description> + The PMIC identifier register contents did not match any known chip. + </description> + <ffdc>TARGET</ffdc> + <ffdc>VENDOR_ID</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_VOLTAGE_OUT_OF_RANGE</rc> + <description> + The voltage from the SPD and offset combination was out of range for the PMIC. + </description> + <ffdc>TARGET</ffdc> + <ffdc>VOLTAGE_BITMAP</ffdc> + <ffdc>RAIL</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_ORDER_OUT_OF_RANGE</rc> + <description> + The sequence order specified by the SPD was out of range for the PMIC (max 4) + </description> + <ffdc>TARGET</ffdc> + <ffdc>RAIL</ffdc> + <ffdc>ORDER</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_DELAY_OUT_OF_RANGE</rc> + <description> + The sequence delay specified by the SPD was out of range for the PMIC (max bitmap: 0b111) + </description> + <ffdc>TARGET</ffdc> + <ffdc>RAIL</ffdc> + <ffdc>DELAY</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_DIMM_SPD_4U</rc> + <description> + The module_height attribute SPD of this DIMM was read as 4U. + 4U is not supported yet for pmic_enable(). + </description> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + </hwpErrors> |
