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authorSumit Kumar <sumit_kumar@in.ibm.com>2017-07-05 05:37:12 -0500
committerChristian R. Geddes <crgeddes@us.ibm.com>2018-01-24 11:10:56 -0500
commit9153608879d2d6fa2f383b0f561862847bf26f43 (patch)
tree88adf404321d569740b183f58ae1f9fc180ab158 /src/import/chips/common
parentc1d8f52bb2960b307624027ae6c70f0c38c374d5 (diff)
downloadtalos-hostboot-9153608879d2d6fa2f383b0f561862847bf26f43.tar.gz
talos-hostboot-9153608879d2d6fa2f383b0f561862847bf26f43.zip
Moving DD specific ring coord from TOR to XIP (step 1)
Step 1 - Ensuring backwards compatibility in TOR and XIP APIs to avoid co-req issue. - Updated TOR and XIP APIs, xip_tool and ipl_build to handle both types of DD coordination. Key_Cronus_Test=XIP_REGRESS HW-Image-Prereq=51511 - 51511 changes the .rings section DD level packaging. This commit (42751) prepares the TOR API and associated codes to handle the new .rings layout while also making the TOR API backwards compatible to the existing .rings section. Change-Id: I7d254340808ca9270fc1c96414102794fcffeabe Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42751 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43259 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/common')
-rw-r--r--src/import/chips/common/utils/imageProcs/common_ringId.H55
1 files changed, 35 insertions, 20 deletions
diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.H b/src/import/chips/common/utils/imageProcs/common_ringId.H
index a8bd93761..a042d5d50 100644
--- a/src/import/chips/common/utils/imageProcs/common_ringId.H
+++ b/src/import/chips/common/utils/imageProcs/common_ringId.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2017 */
+/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -29,9 +29,11 @@
#include <stdint.h>
#include <stddef.h>
+#define TORV3_SUPPORT
-////////////////////////////////////////////////////////////////////////////////
-// Declare assumptions - Begin
+///////////////////////////////////////////////////////////////////////////////
+// Declare assumptions - Begin //
+// //
//
// Various data type defs for enums. Serves following purposes:
@@ -48,40 +50,49 @@ typedef uint8_t ChipType_t; // Type for ChipType enum
typedef uint8_t RingType_t; // Type for RingType enum
typedef uint8_t RingVariant_t; // Type for RingVariant enum
typedef uint32_t TorCpltOffset_t; // Type for offset value to chiplet's CMN or INST section
+typedef uint8_t myBoolean_t; // false:0, true:1, undefined:UNDEFINED_BOOLEAN
#define UNDEFINED_RING_ID (RingId_t)0xffff
#define INVALID_RING_TYPE (RingType_t)0xff
#define INVALID_CHIPLET_TYPE (ChipletType_t)0xff
+#define UNDEFINED_PPE_TYPE (PpeType_t)0xff
#define UNDEFINED_CHIP_TYPE (ChipType_t)0xff
#define MAX_TOR_RING_OFFSET (uint16_t)(256*256-1) // Max val of uint16
#define MAX_RING_NAME_LENGTH (uint8_t)50
#define UNDEFINED_DD_LEVEL (uint8_t)0xff
+#define UNDEFINED_BOOLEAN (myBoolean_t)0xff
-//
-// Declare assumptions - End
+// //
+// Declare assumptions - End //
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
-// TOR layout definitions - Begin
-//
+// TOR layout definitions - Begin //
+// //
//
// TOR header field (appears in top of every HW, SBE, CEN, OVRD, etc ring section)
//
typedef struct
{
- uint32_t magic;
- uint8_t version;
+ uint32_t magic; // =TOR_MAGIC_xyz
+ uint8_t version; // =TOR_VERSION
ChipType_t chipType; // Value from ChipType enum
+#ifdef TORV3_SUPPORT
uint8_t ddLevel; // =0xff if MAGIC_HW, >0 all other MAGICs
uint8_t numDdLevels; // >0 if MAGIC_HW, =1 all other MAGICs
- uint32_t size; // Size of the TOR ringSection.
+#else
+ uint8_t ddLevel; // Actual DD level of ringSection
+ uint8_t undefined;
+#endif
+ uint32_t size; // Size of ringSection.
} TorHeader_t;
//
// Subsequent TOR fields (listed in order they appear in TOR ringSections)
//
+#ifdef TORV3_SUPPORT
typedef struct
{
uint32_t offset;
@@ -89,6 +100,7 @@ typedef struct
uint8_t ddLevel;
uint8_t reserved[3];
} TorDdBlock_t;
+#endif
typedef struct
{
@@ -104,16 +116,19 @@ typedef struct
typedef uint16_t TorRingOffset_t; // Offset value to actual ring
-//
-// TOR layout definitions - End
+// //
+// TOR layout definitions - End //
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
-// Key TOR constants - Begin
-//
+// Key TOR constants - Begin //
+// //
-#define TOR_VERSION 4
+//#define TOR_VERSION 1 // Initial version. Large RS4 header.
+//#define TOR_VERSION 2 // Reduced RS4 header.
+//#define TOR_VERSION 3 // Added TOR magic header.
+#define TOR_VERSION 4 // TOR API code restructuring.
// TOR Magic values for top-level TOR ringSection and sub-ringSections
enum TorMagicNum
@@ -128,8 +143,8 @@ enum TorMagicNum
TOR_MAGIC_CEN = (uint32_t)0x544F524E, // "TORN"
};
-//
-// Key TOR constants - End
+// //
+// Key TOR constants - End //
///////////////////////////////////////////////////////////////////////////////
@@ -192,9 +207,9 @@ typedef struct
// order with which they appear in the HW image's .rings section.
enum PpeType
{
- PT_SBE = 0x00,
- PT_CME = 0x01,
- PT_SGPE = 0x02,
+ PT_SBE = 0x00,
+ PT_CME = 0x01,
+ PT_SGPE = 0x02,
NUM_PPE_TYPES = 0x03
};
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