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| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-07-30 10:43:56 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-08-02 08:38:59 -0500 |
| commit | ea861ac8618f52275bb47565237c3faf974a003e (patch) | |
| tree | 634ec3f3f87b56a8a94ccabaad11dc952ca2aeef /src/import/chips/centaur | |
| parent | 3dcbd232eb5d9db7a882362a5e740a664bb6205e (diff) | |
| download | talos-hostboot-ea861ac8618f52275bb47565237c3faf974a003e.tar.gz talos-hostboot-ea861ac8618f52275bb47565237c3faf974a003e.zip | |
Disables training advanced by default p9c
Change-Id: Ic4e33d1a950716879521444abf633287290b9c52
CQ:SW440238
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63541
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANUWAT SAETOW <asaetow@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63552
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur')
| -rwxr-xr-x | src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C | 6 | ||||
| -rw-r--r-- | src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C index c0f6f9195..6a265034f 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C @@ -190,6 +190,12 @@ fapi2::ReturnCode p9c_mss_draminit_training_advanced(const fapi2::Target<fapi2:: FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_VREF_CAL_CNTL, l_target_centaur, vref_cal_control)); FAPI_INF("%s +++++++++++ - DDR4 - CAL Control - %d ++++++++++++++++++++", mss::c_str(i_target_mba), vref_cal_control); + // Skips training advanced completely if VREF cal control is disable + if(vref_cal_control == fapi2::ENUM_ATTR_CEN_MSS_VREF_CAL_CNTL_DISABLE) + { + FAPI_INF("%s has training advanced disabled, skipping it.", mss::c_str(i_target_mba)); + return fapi2::FAPI2_RC_SUCCESS; + } //const fapi::Target is centaur.mba FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_NUM_RANKS_PER_DIMM, i_target_mba, l_num_ranks_per_dimm)); diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index d532c13e9..dbf3b0d4c 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -122,11 +122,11 @@ Set by: PLL settings written by Dave Cadigan</description> <id>ATTR_CEN_MSS_VREF_CAL_CNTL</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=P8_DRAM - Enable V-Ref Train DRAM Level (P8 algorithm); 0x02=P8_RANK Level Training (P8 algorithm); 0x03=Box shmoo; 0x04=Ternary shmoo - Default Value = 0x03 for box shmoo on all platforms + Default Value = 0x00 for disabling training advanced on all platforms </description> <valueType>uint8</valueType> <enum>DISABLE = 0, P8_DRAM = 1, P8_RANK = 2, BOX = 3, TERNARY = 4</enum> - <default>3</default> + <default>0</default> <platInit/> <odmVisable/> <odmChangeable/> |
