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| author | Louis Stermole <stermole@us.ibm.com> | 2018-10-29 07:59:00 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-11-05 11:27:05 -0600 |
| commit | b26e6d85c0307ee42574a035a9f8743fd7233c9c (patch) | |
| tree | 631488d2ecc187ae1655c5ca258217314ca37ab8 /src/import/chips/centaur | |
| parent | 74aed5ff82cbb9cb106e546daedf44f7d7299846 (diff) | |
| download | talos-hostboot-b26e6d85c0307ee42574a035a9f8743fd7233c9c.tar.gz talos-hostboot-b26e6d85c0307ee42574a035a9f8743fd7233c9c.zip | |
Fix RCD parity errors in p9c row repair
Change-Id: Iacab1aa7217348fea12b0c4b1619594f9d45c2c6
CQ:SW449381
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68099
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Devon A. Baughen <devon.baughen1@ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68103
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur')
3 files changed, 13 insertions, 11 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C index ea16424b3..40dfa37ac 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C @@ -2609,7 +2609,7 @@ fapi2::ReturnCode setup_b_side_ccs(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& } // Only corresponding CS to rank - access_address l_addr = {0, 0, i_mrank, i_srank, 0, 0}; + access_address l_addr = {0, 0, i_mrank, i_srank, 0, i_port}; FAPI_TRY(cs_decode(i_target, l_addr, l_dram_stack[i_port][l_dimm], l_csn_8)); FAPI_TRY(mss_disable_cid(i_target, l_csn_8, l_cke_4)); diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C index 16f7af1cc..d01c3ccb6 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C @@ -89,14 +89,14 @@ extern "C" { FAPI_INF( "%s +++ Check RCD protect time on RDIMM and LRDIMM +++", mss::c_str(i_target)); FAPI_TRY(mss_check_RCD_protect_time(l_mba), "---Error During Check RCD protect time"); - //Step Two.2: Enable address inversion on each MBA for ALL CARDS - FAPI_INF( "%s +++ Setting up adr inversion for port 1 +++", mss::c_str(i_target)); - FAPI_TRY(mss_enable_addr_inversion(l_mba), "---Error During ADR Inversion"); - - //Step Two.3: Apply row repairs on each MBA's DIMM + //Step Two.2: Apply row repairs on each MBA's DIMM FAPI_INF( "%s +++ Applying sPPR row repairs +++", mss::c_str(i_target)); FAPI_TRY(p9c_mss_deploy_row_repairs(l_mba), "---Error During Row Reapirs"); + //Step Two.3: Enable address inversion on each MBA for ALL CARDS + FAPI_INF( "%s +++ Setting up adr inversion for port 1 +++", mss::c_str(i_target)); + FAPI_TRY(mss_enable_addr_inversion(l_mba), "---Error During ADR Inversion"); + // Step Three: Enable Refresh FAPI_INF( "%s +++ Enabling Refresh +++", mss::c_str(i_target)); FAPI_TRY(fapi2::getScom(l_mba, CEN_MBA_MBAREF0Q, l_mba01_ref0q_data_buffer_64)); diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C index ebd58f40d..823699902 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C @@ -92,6 +92,7 @@ extern "C" access_address l_enable_sppr = l_addr; fapi2::variable_buffer l_data_16(16); fapi2::variable_buffer l_bank_3(3); + fapi2::buffer<uint64_t> l_modeq_orig; fapi2::buffer<uint64_t> l_row; fapi2::buffer<uint64_t> l_bank; fapi2::buffer<uint64_t> l_saved_mr0; @@ -169,6 +170,7 @@ extern "C" // Enable CCS and set RAS/CAS/WE high during idles FAPI_DBG("%s Enabling CCS", mss::c_str(i_target_mba)); FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_CCS_MODEQ, l_reg_buffer)); + l_modeq_orig = l_reg_buffer; FAPI_TRY(l_reg_buffer.setBit(29)); //Enable CCS FAPI_TRY(l_reg_buffer.setBit(51)); //ACT high FAPI_TRY(l_reg_buffer.setBit(52)); //RAS high @@ -251,9 +253,7 @@ extern "C" // Disable CCS FAPI_DBG("%s Disabling CCS", mss::c_str(i_target_mba)); - FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_CCS_MODEQ, l_reg_buffer)); - FAPI_TRY(l_reg_buffer.clearBit(29)); - FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_CCS_MODEQ, l_reg_buffer)); + FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_CCS_MODEQ, l_modeq_orig)); // Turn on refresh FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_reg_buffer)); @@ -553,6 +553,8 @@ extern "C" l_port_rank = (l_dimm_index * MAX_RANKS_PER_DIMM) + l_mrank; + FAPI_INF("%s Deploying row repair on all DRAMs on mrank %d, srank %d, bg %d, bank %d, row 0x%05x", + mss::spd::c_str(l_dimm), l_mrank, l_srank, l_bg, l_bank, l_row); FAPI_TRY(p9c_mss_row_repair(i_target_mba, l_port, l_port_rank, l_srank, l_bg, l_bank, l_row, l_dram_bitmap)); } } @@ -692,8 +694,8 @@ extern "C" } // Deploy row repair and clear bad DQs - FAPI_INF("%s Deploying row repair on DRAM %d, mrank %d, srank %d, bg %d, bank %d, row 0x%05x", - mss::spd::c_str(l_dimm), l_dram, l_rank, l_srank, l_bg, l_bank, l_row); + FAPI_INF("%s Deploying row repair on port %d, DRAM %d, mrank %d, srank %d, bg %d, bank %d, row 0x%05x", + mss::spd::c_str(l_dimm), l_port, l_dram, l_rank, l_srank, l_bg, l_bank, l_row); FAPI_TRY(l_dram_bitmap.setBit(DRAM_START_BIT + l_dram)); FAPI_TRY(p9c_mss_row_repair(i_target_mba, l_port, l_port_rank, l_srank, l_bg, l_bank, l_row, l_dram_bitmap)); |
