nest updates for p9c DD1.3 native and p9c DD1.2 compatibility modes

  HW 446279 - disable update for compat and native modes
  HW 439321 - disable update for compat, enable for native mode
  HW 443004 - disable update for compat and native modes
  HW 446453 - disable update for compat, enable for native mode

Change-Id: I3dd1ed6075ff473adbaf342671dd977c53fb2f06
CQ: HW446279
CQ: HW439321
CQ: HW443004
CQ: HW446453
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64067
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64084
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

6 files changed, 65 insertions, 18 deletions

diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.C b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.C
index 28a96a81d..eb88947e8 100644
--- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.C
+++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.C
@@ -42,7 +42,10 @@ constexpr uint64_t literal_0b0011000 = 0b0011000;
 constexpr uint64_t literal_0b0010001 = 0b0010001;
 constexpr uint64_t literal_0b00 = 0b00;
 constexpr uint64_t literal_0b11 = 0b11;
+constexpr uint64_t literal_0x1 = 0x1;
+constexpr uint64_t literal_0x0 = 0x0;
 constexpr uint64_t literal_0b1000000 = 0b1000000;
+constexpr uint64_t literal_0b0001111 = 0b0001111;
 constexpr uint64_t literal_0b101 = 0b101;
 constexpr uint64_t literal_0b0111 = 0b0111;
 constexpr uint64_t literal_0b0011 = 0b0011;
@@ -64,17 +67,22 @@ constexpr uint64_t literal_0b0010110 = 0b0010110;
 constexpr uint64_t literal_0b1000110 = 0b1000110;
 
 fapi2::ReturnCode centaur_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& TGT0,
-                                   const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1)
+                                   const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2)
 {
     {
         fapi2::ATTR_EC_Type   l_chip_ec;
         fapi2::ATTR_NAME_Type l_chip_id;
-        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id));
-        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec));
+        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT2, l_chip_id));
+        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec));
         fapi2::ATTR_IS_SIMULATION_Type l_TGT1_ATTR_IS_SIMULATION;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, TGT1, l_TGT1_ATTR_IS_SIMULATION));
         uint64_t l_def_IS_HW = (l_TGT1_ATTR_IS_SIMULATION == literal_0);
         uint64_t l_def_IS_SIM = (l_TGT1_ATTR_IS_SIMULATION == literal_1);
+        fapi2::ATTR_RISK_LEVEL_Type l_TGT1_ATTR_RISK_LEVEL;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, TGT1, l_TGT1_ATTR_RISK_LEVEL));
+        fapi2::ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13, TGT2,
+                               l_TGT2_ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13));
         fapi2::ATTR_EI_BUS_TX_MSBSWAP_Type l_TGT0_ATTR_EI_BUS_TX_MSBSWAP;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EI_BUS_TX_MSBSWAP, TGT0, l_TGT0_ATTR_EI_BUS_TX_MSBSWAP));
         fapi2::buffer<uint64_t> l_scom_buffer;
@@ -588,9 +596,28 @@ fapi2::ReturnCode centaur_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x8009d8000201043full, l_scom_buffer ));
 
-            l_scom_buffer.insert<48, 7, 57, uint64_t>(literal_0b1000000 );
-            constexpr auto l_DMI_RX_RXCTL_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP2 = 0x2;
-            l_scom_buffer.insert<55, 4, 60, uint64_t>(l_DMI_RX_RXCTL_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP2 );
+            if (((( ! l_TGT2_ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13) || (l_TGT1_ATTR_RISK_LEVEL == literal_0x0))
+                 || (l_TGT1_ATTR_RISK_LEVEL == literal_0x1)))
+            {
+                l_scom_buffer.insert<48, 7, 57, uint64_t>(literal_0b1000000 );
+            }
+            else if (( true ))
+            {
+                l_scom_buffer.insert<48, 7, 57, uint64_t>(literal_0b0001111 );
+            }
+
+            if (((( ! l_TGT2_ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13) || (l_TGT1_ATTR_RISK_LEVEL == literal_0x0))
+                 || (l_TGT1_ATTR_RISK_LEVEL == literal_0x1)))
+            {
+                constexpr auto l_DMI_RX_RXCTL_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP2 = 0x2;
+                l_scom_buffer.insert<55, 4, 60, uint64_t>(l_DMI_RX_RXCTL_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP2 );
+            }
+            else if (( true ))
+            {
+                constexpr auto l_DMI_RX_RXCTL_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP7 = 0x7;
+                l_scom_buffer.insert<55, 4, 60, uint64_t>(l_DMI_RX_RXCTL_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP7 );
+            }
+
             l_scom_buffer.insert<61, 3, 61, uint64_t>(literal_0b101 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x8009d8000201043full, l_scom_buffer));
         }
diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.H b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.H
index b87464dc7..564bf8f60 100644
--- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.H
+++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_dmi_scom.H
@@ -32,13 +32,13 @@
 
 
 typedef fapi2::ReturnCode (*centaur_dmi_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>&,
-        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&);
+        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
 
 extern "C"
 {
 
     fapi2::ReturnCode centaur_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& TGT0,
-                                       const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1);
+                                       const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2);
 
 }
 
diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.C b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.C
index 5a5a803eb..ae02abd32 100644
--- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.C
+++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.C
@@ -34,6 +34,8 @@ constexpr uint64_t literal_0b0 = 0b0;
 constexpr uint64_t literal_0b0000000 = 0b0000000;
 constexpr uint64_t literal_0x0 = 0x0;
 constexpr uint64_t literal_0b00000 = 0b00000;
+constexpr uint64_t literal_0x1 = 0x1;
+constexpr uint64_t literal_0b1 = 0b1;
 constexpr uint64_t literal_0b010010 = 0b010010;
 constexpr uint64_t literal_0b00 = 0b00;
 constexpr uint64_t literal_0b00000000000000000000 = 0b00000000000000000000;
@@ -64,7 +66,6 @@ constexpr uint64_t literal_8 = 8;
 constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_4 = 4;
 constexpr uint64_t literal_0b01 = 0b01;
-constexpr uint64_t literal_0b1 = 0b1;
 constexpr uint64_t literal_13 = 13;
 constexpr uint64_t literal_10 = 10;
 constexpr uint64_t literal_12 = 12;
@@ -117,13 +118,20 @@ constexpr uint64_t literal_0xAA = 0xAA;
 
 fapi2::ReturnCode centaur_mbs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& TGT0,
                                    const fapi2::Target<fapi2::TARGET_TYPE_MBA>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_L4>& TGT2,
-                                   const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT3)
+                                   const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT3, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT4)
 {
     {
         fapi2::ATTR_EC_Type   l_chip_ec;
         fapi2::ATTR_NAME_Type l_chip_id;
-        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id));
-        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec));
+        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT4, l_chip_id));
+        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT4, l_chip_ec));
+        fapi2::ATTR_RISK_LEVEL_Type l_TGT3_ATTR_RISK_LEVEL;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, TGT3, l_TGT3_ATTR_RISK_LEVEL));
+        fapi2::ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13_Type l_TGT4_ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13, TGT4,
+                               l_TGT4_ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13));
+        uint64_t l_def_hw439321_wa = ((( ! l_TGT4_ATTR_CHIP_EC_FEATURE_HW439321_FIXED_IN_P9UDD13)
+                                       || (l_TGT3_ATTR_RISK_LEVEL == literal_0x0)) || (l_TGT3_ATTR_RISK_LEVEL == literal_0x1));
         fapi2::ATTR_CEN_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT_Type l_TGT0_ATTR_CEN_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT, TGT0,
                                l_TGT0_ATTR_CEN_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT));
@@ -784,10 +792,14 @@ fapi2::ReturnCode centaur_mbs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF
                 l_scom_buffer.insert<21, 5, 59, uint64_t>(literal_0b00000 );
             }
 
-            if (literal_1)
+            if ((l_def_hw439321_wa == literal_1))
             {
                 l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0b0 );
             }
+            else if (literal_1)
+            {
+                l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0b1 );
+            }
 
             if (literal_1)
             {
diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.H b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.H
index 40d761d27..b6b80fba0 100644
--- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.H
+++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mbs_scom.H
@@ -33,14 +33,14 @@
 
 typedef fapi2::ReturnCode (*centaur_mbs_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>&,
         const fapi2::Target<fapi2::TARGET_TYPE_MBA>&, const fapi2::Target<fapi2::TARGET_TYPE_L4>&,
-        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&);
+        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
 
 extern "C"
 {
 
     fapi2::ReturnCode centaur_mbs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& TGT0,
                                        const fapi2::Target<fapi2::TARGET_TYPE_MBA>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_L4>& TGT2,
-                                       const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT3);
+                                       const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT3, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT4);
 
 }
 
diff --git a/src/import/chips/centaur/procedures/hwp/io/p9_io_cen_scominit.C b/src/import/chips/centaur/procedures/hwp/io/p9_io_cen_scominit.C
index d307c8834..86c8c3183 100644
--- a/src/import/chips/centaur/procedures/hwp/io/p9_io_cen_scominit.C
+++ b/src/import/chips/centaur/procedures/hwp/io/p9_io_cen_scominit.C
@@ -75,8 +75,13 @@ fapi2::ReturnCode p9_io_cen_scominit(const CEN_TGT& i_tgt)
     // Get system target
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> sys_tgt;
 
+    // Get attached processor target
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> proc_tgt = i_tgt.
+            getParent<fapi2::TARGET_TYPE_DMI>().
+            getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+
     FAPI_INF("Invoke FAPI procedure core: input_target");
-    FAPI_EXEC_HWP(rc, centaur_dmi_scom, i_tgt, sys_tgt);
+    FAPI_EXEC_HWP(rc, centaur_dmi_scom, i_tgt, sys_tgt, proc_tgt);
 
     if(rc)
     {
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C
index d43823c77..b78db53e9 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -58,6 +58,9 @@ extern "C" {
         // Get a vector of the functional MBA targets
         const auto l_mba_targets = i_target.getChildren<fapi2::TARGET_TYPE_MBA>();
         const auto l_l4_targets = i_target.getChildren<fapi2::TARGET_TYPE_L4>(fapi2::TARGET_STATE_PRESENT);
+        const auto l_proc_target = i_target.
+                                   getParent<fapi2::TARGET_TYPE_DMI>().
+                                   getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
 
         FAPI_ASSERT(l_l4_targets.size() > 0,
                     fapi2::CEN_MSS_SCOMINIT_NUM_L4_ERROR().
@@ -91,7 +94,7 @@ extern "C" {
         for (const auto& mba : l_mba_targets)
         {
             FAPI_DBG("Running MBS scom initfile\n");
-            FAPI_EXEC_HWP(l_rc, centaur_mbs_scom, i_target, mba, l_l4_targets[0], FAPI_SYSTEM);
+            FAPI_EXEC_HWP(l_rc, centaur_mbs_scom, i_target, mba, l_l4_targets[0], FAPI_SYSTEM, l_proc_target);
 
             if (l_rc)
             {