MRW attribute changes

Change-Id: I78b2f33d144df826fd007914e378b6dd135fbd3d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48207
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48633
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

7 files changed, 40 insertions, 130 deletions

diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C
index f2cd0b467..5773995af 100644
--- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C
+++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C
@@ -1261,9 +1261,8 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>&
         l_TGT2_ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, TGT2,
                                l_TGT2_ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP));
-        fapi2::ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR_Type l_TGT2_ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR, TGT2,
-                               l_TGT2_ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR));
+        fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS_Type l_TGT2_ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS, TGT2, l_TGT2_ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS));
         fapi2::ATTR_CEN_EFF_DRAM_TRFC_Type l_TGT0_ATTR_CEN_EFF_DRAM_TRFC;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_TRFC, TGT0, l_TGT0_ATTR_CEN_EFF_DRAM_TRFC));
         fapi2::ATTR_CEN_EFF_NUM_RANKS_PER_DIMM_Type l_TGT0_ATTR_CEN_EFF_NUM_RANKS_PER_DIMM;
@@ -6276,7 +6275,7 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>&
 
             if (literal_1)
             {
-                l_scom_buffer.insert<42, 14, 50, uint64_t>(l_TGT2_ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR );
+                l_scom_buffer.insert<42, 14, 50, uint64_t>(l_TGT2_ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS );
             }
 
             if (literal_1)
@@ -6286,7 +6285,7 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>&
 
             if (literal_1)
             {
-                l_scom_buffer.insert<42, 14, 50, uint64_t>(l_TGT2_ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR );
+                l_scom_buffer.insert<42, 14, 50, uint64_t>(l_TGT2_ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS );
             }
 
             if (literal_1)
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C
index 352057ba3..ceb3779bf 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C
@@ -123,9 +123,9 @@ extern "C" {
 
         // get input attributes
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CUSTOM_DIMM, i_target_mba,  l_custom_dimm));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MAX_DRAM_DATABUS_UTIL,
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_max_dram_databus_util));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
                                l_throttle_d));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_MEM_WATT_TARGET,
                                i_target_mba, l_channel_pair_watt_target));
@@ -139,9 +139,9 @@ extern "C" {
         // other attributes for custom dimms to get
         if (l_custom_dimm == fapi2::ENUM_ATTR_CEN_EFF_CUSTOM_DIMM_YES)
         {
-            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT,
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT,
                                    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_power_curve_percent_uplift));
-            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE,
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE,
                                    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_power_curve_percent_uplift_idle));
             FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_TOTAL_POWER_SLOPE,
                                    i_target_mba, l_total_power_slope_array));
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C
index cd2448783..b30946cf8 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C
@@ -432,17 +432,17 @@ extern "C" {
                                i_target_mba, l_num_dimms_on_port));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_THERMAL_MEMORY_POWER_LIMIT,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_dimm_thermal_power_limit));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
                                l_runtime_throttle_d));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MAX_DRAM_DATABUS_UTIL,
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_max_dram_databus_util));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM,
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_dimm_reg_power_limit_per_dimm));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4,
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_dimm_reg_power_limit_per_dimm_ddr4));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR,
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_max_number_dimms_per_reg));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE,
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_dimm_reg_power_limit_adj_enable));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_reg_max_dimm_count));
@@ -516,7 +516,7 @@ extern "C" {
 
         l_dimm_reg_power_limit_per_dimm_adj = l_dimm_reg_power_limit_per_dimm;
 
-        if (l_dimm_reg_power_limit_adj_enable == fapi2::ENUM_ATTR_CEN_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE_TRUE)
+        if (l_dimm_reg_power_limit_adj_enable == fapi2::ENUM_ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE_TRUE)
         {
             // adjust reg power limit per cdimm only if l_reg_max_dimm_count>0 and l_reg_max_dimm_count<l_max_number_dimms_per_reg
             if (
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_mb_interleave.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_mb_interleave.C
index 28494ee81..2093ca8da 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_mb_interleave.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_mb_interleave.C
@@ -336,7 +336,7 @@ extern "C" {
                 case fapi2::ENUM_ATTR_CEN_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL_REQUIRED:
                     if(l_size[0] != l_size[1])
                     {
-                        FAPI_ERR("ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL is REQUIRED, but size on l_side 0 does not match size on l_side 1 sizes %d %d",
+                        FAPI_ERR("ATTR_CEN_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL is REQUIRED, but size on l_side 0 does not match size on l_side 1 sizes %d %d",
                                  l_size[0], l_size[1]);
                         l_mss_derived_mba_cacheline_interleave_mode = fapi2::ENUM_ATTR_CEN_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_OFF;
                         l_mss_mba_addr_interleave_bit = 0;
@@ -379,7 +379,7 @@ extern "C" {
                     break;
 
                 default:
-                    FAPI_ERR("Internal Error: ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL is not a known value");
+                    FAPI_ERR("Internal Error: ATTR_CEN_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL is not a known value");
                     l_mss_derived_mba_cacheline_interleave_mode = fapi2::ENUM_ATTR_CEN_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_OFF;
                     l_mss_mba_addr_interleave_bit = 0;
                     break;
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_thermal_init.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_thermal_init.C
index 78edb5767..7217a778c 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_thermal_init.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_thermal_init.C
@@ -139,8 +139,8 @@ extern "C" {
         else
         {
             // sensor cache address map for non custom dimm temperature sensors (which i2c bus and i2c address they are)
-            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MEM_SENSOR_CACHE_ADDR_MAP, i_target,  l_dimm_sensor_cache_addr_map),
-                     "Failed to get attr ATTR_CEN_MRW_MEM_SENSOR_CACHE_ADDR_MAP on %s", mss::c_str(i_target));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, i_target,  l_dimm_sensor_cache_addr_map),
+                     "Failed to get attr ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP on %s", mss::c_str(i_target));
         }
 
         // Configure Centaur Thermal Cache
@@ -411,7 +411,7 @@ extern "C" {
                                    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
                                    l_safemode_throttle_n_per_chip));
 
-            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR,
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS,
                                    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
                                    l_throttle_d));
 
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml
index 7447b069b..d3254e2ed 100644
--- a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml
+++ b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml
@@ -2938,20 +2938,6 @@ Comes from the VPD MW Keyword</description>
 </attribute>
 
 <attribute>
-    <id>ATTR_CEN_L4_BANK_DELETE_VPD</id>
-    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
-    <description>L4 Bank Delete settings in VPD.
-Denotes what banks have been deleted from the L4.
-Data will be pulled from CDIMM VPD if CDIMM present.
-Data will be pulled from backplane VPD if IS DIMMs present.</description>
-    <valueType>uint32</valueType>
-    <writeable/>
-    <platInit/>
-    <odmVisable/>
-    <persistent/>
-</attribute>
-
-<attribute>
     <id>ATTR_CEN_VPD_MT_VERSION_BYTE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Describes the Version of MT Keyword</description>
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
index 29e82be6a..6744193b7 100644
--- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
+++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
@@ -2101,15 +2101,6 @@ firmware notes: none</description>
     <persistRuntime/>
 </attribute>
 
-<attribute>
-    <id>ATTR_CEN_MRW_THERMAL_MEMORY_POWER_LIMIT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook Thermal Memory Power Limit</description>
-    <valueType>uint32</valueType>
-    <platInit/>
-    <odmVisable/>
-</attribute>
-
 <!--
 <attribute>
     <id>ATTR_CEN_MSS_INTERLEAVE_ENABLE</id>
@@ -3045,35 +3036,6 @@ Will be set at an MBA level with one policy to be used</description>
 -->
 
 <attribute>
-    <id>ATTR_CEN_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook DIMM power curve percent uplift for this system at max utilization.</description>
-    <valueType>uint8</valueType>
-    <platInit/>
-    <odmVisable/>
-    <persistRuntime/>
-</attribute>
-
-<attribute>
-    <id>ATTR_CEN_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook DIMM power curve percent uplift for this system at idle utilization.</description>
-    <valueType>uint8</valueType>
-    <platInit/>
-    <odmVisable/>
-    <persistRuntime/>
-</attribute>
-
-<attribute>
-    <id>ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description>
-    <valueType>uint32</valueType>
-    <platInit/>
-    <odmVisable/>
-    <persistRuntime/>
-</attribute>
-<attribute>
     <id>ATTR_CEN_MSS_INIT_STATE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>How far into the ipl istep the centaur has been brought up</description>
@@ -3085,16 +3047,6 @@ Will be set at an MBA level with one policy to be used</description>
 </attribute>
 
 <attribute>
-    <id>ATTR_CEN_MRW_MAX_DRAM_DATABUS_UTIL</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%).  Used to determine memory throttle values.</description>
-    <valueType>uint32</valueType>
-    <platInit/>
-    <odmVisable/>
-    <persistRuntime/>
-</attribute>
-
-<attribute>
     <id>ATTR_CEN_MSS_EFF_VPD_VERSION</id>
     <targetType>TARGET_TYPE_MBA</targetType>
     <description>
@@ -3176,6 +3128,25 @@ Will be set at an MBA level with one policy to be used</description>
     <odmVisable/>
 </attribute>
 
+<attribute>
+    <id>ATTR_CEN_MRW_THERMAL_MEMORY_POWER_LIMIT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook Thermal Memory Power Limit</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MRW_POWER_CONTROL_REQUESTED</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Capable power control settings. In MRW.</description>
+    <valueType>uint8</valueType>
+    <enum>OFF = 0x00, SLOWEXIT = 0x01, FASTEXIT = 0x02</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
 <!--
 <attribute>
     <id>ATTR_CEN_MSS_AVDD_OFFSET_DISABLE</id>
@@ -3433,16 +3404,6 @@ Will be set at an MBA level with one policy to be used</description>
 </attribute>
 -->
 
-<attribute>
-    <id>ATTR_CEN_MRW_POWER_CONTROL_REQUESTED</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Capable power control settings. In MRW.</description>
-    <valueType>uint8</valueType>
-    <enum>OFF = 0x00, SLOWEXIT = 0x01, FASTEXIT = 0x02</enum>
-    <platInit/>
-    <odmVisable/>
-</attribute>
-
 <!--
 <attribute>
     <id>ATTR_CEN_MSS_AVDD_OFFSET</id>
@@ -3568,7 +3529,7 @@ Will be set at an MBA level with one policy to be used</description>
 -->
 
 <attribute>
-    <id>ATTR_CEN_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id>
+    <id>ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Machine Readable Workbook value detailing the wiring of the 8 dimm temperature sensors for non custom dimms, in DIMM A0,A1,B0,B1,C0,C1,D0,D1 order. One nibble per sensor where bit0 (MSB) is the i2c bus the sensor is attached to (0 for master, 1 for spare) and bits 1:3 are for A2,A1,A0 of the sensor i2c address (where A2 is MSB)</description>
     <valueType>uint32</valueType>
@@ -3587,42 +3548,6 @@ Will be set at an MBA level with one policy to be used</description>
 </attribute>
 
 <attribute>
-    <id>ATTR_CEN_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook enablement of the HWP code to adjust the VMEM regulator power limit based on number of installed DIMMs.</description>
-    <valueType>uint8</valueType>
-    <platInit/>
-    <enum>FALSE = 0, TRUE = 1</enum>
-    <odmVisable/>
-</attribute>
-
-<attribute>
-    <id>ATTR_CEN_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook value for the maximum possible number of dimms that can be installed under any of the VMEM regulators.</description>
-    <valueType>uint8</valueType>
-    <platInit/>
-    <odmVisable/>
-</attribute>
-
-<attribute>
-    <id>ATTR_CEN_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook DDR3 VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW.</description>
-    <valueType>uint32</valueType>
-    <platInit/>
-    <odmVisable/>
-</attribute>
-<attribute>
-    <id>ATTR_CEN_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>Machine Readable Workbook DDR4 VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW.</description>
-    <valueType>uint32</valueType>
-    <platInit/>
-    <odmVisable/>
-</attribute>
-
-<attribute>
     <id>ATTR_CEN_MRW_WR_VREF_CHECK_VREF_STEP_SIZE</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>Machine Readable Workbook attribute that holds the step size of the VREF when doing a box shmoo</description>