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| author | Dan Crowell <dcrowell@us.ibm.com> | 2017-11-16 13:54:18 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-12-01 11:37:10 -0500 |
| commit | 453d38aa29e476cee111bd82e91cbc64c0a1b53c (patch) | |
| tree | 82601d65a7dc821d3a62b3552534aadb2813d892 /src/import/chips/centaur/procedures | |
| parent | 716a165455c1dfbe7a2c4e90026b3e4110309d5c (diff) | |
| download | talos-hostboot-453d38aa29e476cee111bd82e91cbc64c0a1b53c.tar.gz talos-hostboot-453d38aa29e476cee111bd82e91cbc64c0a1b53c.zip | |
Revert ATTR_CEN_ECID back to ATTR_ECID
Firmware needs a common attribute for all chip targets
Change-Id: Ia448b73bed691f493c7edb98e675e6febce74d23
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49941
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49945
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures')
| -rw-r--r-- | src/import/chips/centaur/procedures/hwp/memory/p9c_mss_get_cen_ecid.C | 2 | ||||
| -rw-r--r-- | src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml | 13 |
2 files changed, 1 insertions, 14 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_get_cen_ecid.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_get_cen_ecid.C index 82911e7b6..24bcc458a 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_get_cen_ecid.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_get_cen_ecid.C @@ -125,7 +125,7 @@ extern "C" { ecid[0] = ecid_struct.io_ecid[0]; ecid[1] = ecid_struct.io_ecid[1]; - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_ECID, i_target, ecid), "mss_get_cen_ecid: Could not set ATTR_ECID" ); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_ECID, i_target, ecid), "mss_get_cen_ecid: Could not set ATTR_ECID" ); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_CENTAUR_EC_FEATURE_CHECK_L4_CACHE_ENABLE_UNKNOWN, i_target, l_checkL4CacheEnableUnknown), diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index f39b25fd1..29e82be6a 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -2789,19 +2789,6 @@ bits6:7 will be consumed together to form COARSE_LVL. </description> </attribute> <attribute> - <id>ATTR_CEN_ECID</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 -Created from running the mss_get_cen_ecid.C -Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description> - <valueType>uint64</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> - <array> 2</array> -</attribute> - -<attribute> <id>ATTR_CEN_MSS_ALLOW_SINGLE_PORT</id> <targetType>TARGET_TYPE_MBA</targetType> <description>When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes. Used in eff_config</description> |
