diff options
| author | Andre Marin <aamarin@us.ibm.com> | 2017-08-10 09:53:50 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-14 00:13:46 -0400 |
| commit | dea417f070afd93b5fc8e0a00b39660512a0678a (patch) | |
| tree | 5a5e27bde54de910452527d2071dbd2afb4cadb0 /src/import/chips/centaur/procedures/xml | |
| parent | fb053c5e5348eb1f374197255c6cfbe19b26d513 (diff) | |
| download | talos-hostboot-dea417f070afd93b5fc8e0a00b39660512a0678a.tar.gz talos-hostboot-dea417f070afd93b5fc8e0a00b39660512a0678a.zip | |
Replace TARGET_TYPE_MBA_CHIPLET to TARGET_TYPE_MBA, FW request
Change-Id: Ife450796a27e4741a81d39eefa97f3f478f1695d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44478
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44480
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures/xml')
3 files changed, 211 insertions, 211 deletions
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index 7fcef69a5..5bc511607 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -39,7 +39,7 @@ <attributes> <attribute> <id>ATTR_CEN_ZMODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description> Set to activate System Z mode, used to mask opposite port on Mcbist and Schmoos. </description> @@ -50,7 +50,7 @@ <attribute> <id>ATTR_CEN_ZMODE_PORT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description> Used to set the port under test for System Z. Opposite port will be masked from MCBIST/Schmoo </description> @@ -61,7 +61,7 @@ <attribute> <id>ATTR_CEN_EFF_DRAM_ADDRESS_MIRRORING</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description> Ranks that have address mirroring. This data is derived from SPD and C-DIMM VPD. @@ -159,7 +159,7 @@ Set by: PLL settings written by Dave Cadigan</description> <!-- <attribute> <id>ATTR_CEN_MSS_DIMM_MFG_ID_CODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Manufacturer ID Code RCD: bits(31:16), Module: bits(15:0)</description> <valueType>uint32</valueType> <writeable/> @@ -171,7 +171,7 @@ Set by: PLL settings written by Dave Cadigan</description> <attribute> <id>ATTR_CEN_EFF_DIMM_RANKS_CONFIGED</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Dimensions are [port][dimm] A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur. creator: mss_eff_cnfg @@ -187,7 +187,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_NUM_RANKS_PER_DIMM</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. values are 0,1,2, 4 up to 32 creator: mss_eff_cnfg @@ -203,7 +203,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDIC standard. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various @@ -219,7 +219,7 @@ NOTE: Do not use the enum type of CDIMM. Use the attribute EFF_DIMM_CUSTOM to t <attribute> <id>ATTR_CEN_EFF_CUSTOM_DIMM</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DIMM is a custom DIMM. This is commonly known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM. Created in mss_eff_cnfg Use this attribute if you need to know if the Centaur is on the DIMM instead of on a planar.</description> <valueType>uint8</valueType> @@ -233,7 +233,7 @@ Use this attribute if you need to know if the Centaur is on the DIMM instead of <attribute> <id>ATTR_CEN_EFF_DRAM_WIDTH</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DRAM Device Width: X4, X8, X16, X32. Used in various locations and is computed in mss_eff_cnfg. creator: mss_eff_cnfg consumer: various @@ -247,7 +247,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_GEN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Generation of memory: DDR3, DDR4. Used in various locations and is computed in mss_eff_cnfg. creator: mss_eff_cnfg consumer: various @@ -261,7 +261,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -276,7 +276,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -291,7 +291,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -306,7 +306,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_PRIMARY_RANK_GROUP3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -321,7 +321,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -336,7 +336,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -351,7 +351,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -366,7 +366,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SECONDARY_RANK_GROUP3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -381,7 +381,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -396,7 +396,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -411,7 +411,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -426,7 +426,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_TERTIARY_RANK_GROUP3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -441,7 +441,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP0</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -456,7 +456,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP1</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -471,7 +471,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -486,7 +486,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_QUATERNARY_RANK_GROUP3</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_rank_group consumer: various @@ -502,7 +502,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_EFF_DIMM_SPARE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd OBSOLETE: Use ATTR_CEN_VPD_DIMM_SPARE </description> @@ -517,7 +517,7 @@ OBSOLETE: Use ATTR_CEN_VPD_DIMM_SPARE <attribute> <id>ATTR_CEN_EFF_DRAM_WR_VREF</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT) or mss_eff_cnfg_termination consumer: various.C and initfile @@ -535,7 +535,7 @@ This is for DDR3</description> <attribute> <id>ATTR_CEN_EFF_DRAM_WR_VREF_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which VREF to use on the WR Schmoo. The LSB corresponds to the highest WR Vref</description> <valueType>uint32</valueType> <writeable/> @@ -547,7 +547,7 @@ This is for DDR3</description> <!-- <attribute> <id>ATTR_CEN_EFF_DRAM_WRDDR4_VREF_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which VREF to use on the WR Schmoo. The LSB corresponds to the highest WR Vref</description> <valueType>uint32</valueType> <writeable/> @@ -559,7 +559,7 @@ This is for DDR3</description> <attribute> <id>ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Centaur DQ and DQS Drive Impedance Used in various locations and comes from the MT Keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT)/mss_eff_cnfg_termination consumer: initfile,various.C files @@ -577,7 +577,7 @@ OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x <attribute> <id>ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description> <valueType>uint32</valueType> <writeable/> @@ -588,7 +588,7 @@ OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x <attribute> <id>ATTR_CEN_EFF_CEN_DRV_IMP_CLK_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description> <valueType>uint8</valueType> <writeable/> @@ -599,7 +599,7 @@ OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x <attribute> <id>ATTR_CEN_EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description> <valueType>uint8</valueType> <writeable/> @@ -610,7 +610,7 @@ OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x <attribute> <id>ATTR_CEN_EFF_CEN_DRV_IMP_CNTL_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field. This is the nominal value</description> <valueType>uint8</valueType> @@ -623,7 +623,7 @@ This is the nominal value</description> <attribute> <id>ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Centaur DQ and DQS Receiver Impedance Used in various locations and it comes from the VPD MT keyword for custom DIMMs or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD, mss_eff_cnfg_termination Consumer: initfile + C code @@ -640,7 +640,7 @@ This is the nominal value</description> <attribute> <id>ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible receiver termination and start with the first value down to the last (largest) impedance as the LSB of the 32 bit field.</description> <valueType>uint32</valueType> <writeable/> @@ -651,7 +651,7 @@ This is the nominal value</description> <attribute> <id>ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Centaur DQ and DQS Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT), mss_eff_cnfg_termination consumer: initfiles,various.C @@ -672,7 +672,7 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB</description> <valueType>uint8</valueType> <writeable/> @@ -683,7 +683,7 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_CEN_EFF_CEN_SLEW_RATE_CLK_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB</description> <valueType>uint8</valueType> <writeable/> @@ -694,7 +694,7 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_CEN_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB</description> <valueType>uint8</valueType> <writeable/> @@ -705,7 +705,7 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_CEN_EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB</description> <valueType>uint8</valueType> <writeable/> @@ -716,7 +716,7 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_CEN_EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB</description> <valueType>uint8</valueType> <writeable/> @@ -727,7 +727,7 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_CEN_EFF_RD_VREF</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Centaur Read Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Creator: VPD(MT) or mss_eff_cnfg_termination consumer: various.C and initfiles @@ -744,7 +744,7 @@ This is the nominal value</description> <attribute> <id>ATTR_CEN_EFF_CEN_RD_VREF_SCHMOO</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables for which VREF value can be used in timing adjustments. The highest voltage corresponds to the LSB</description> <valueType>uint32</valueType> <writeable/> @@ -755,7 +755,7 @@ This is the nominal value</description> <attribute> <id>ATTR_CEN_EFF_DIMM_SIZE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DIMM Size. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -770,7 +770,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_BANKS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Number of DRAM banks. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -783,7 +783,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_ROWS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Number of DRAM rows. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -796,7 +796,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_COLS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Number of DRAM columns. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -809,7 +809,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_DENSITY</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DRAM Density. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -822,7 +822,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRCD</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RAS to CAS Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -835,7 +835,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRRD</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Row ACT to Row ACT Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -848,7 +848,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRRD_L</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DDR4 - Row to Row:Long timings tRRD_L : bank accesses within the same bank group creator: mss_eff_cnfg_timing consumer: various @@ -861,7 +861,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Row Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -874,7 +874,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRAS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>ACT to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -887,7 +887,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRC</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>ACT to ACT/Refresh Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -900,7 +900,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRFI</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Refresh Interval. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. In unit clock. creator: mss_eff_cnfg_timing consumer: various @@ -913,7 +913,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRFC</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Refresh Recovery Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. In unit clock. creator: mss_eff_cnfg_timing consumer: various @@ -926,7 +926,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TWTR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Internal Write to Read Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -939,7 +939,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TWTR_L</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DDR4 - Long timings (tCCD_L, tRRD_L, and tWTR_L): bank accesses within the same bank group creator: mss_eff_cnfg_timing consumer: various @@ -952,7 +952,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TRTP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Internal Read to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -965,7 +965,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TFAW</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Four ACT Window Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -978,7 +978,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_BL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Burst Length. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -992,7 +992,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_CL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>CAS Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -1005,7 +1005,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_AL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Additive Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -1019,7 +1019,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_CWL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>CAS Write Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -1032,7 +1032,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_RBT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Read Burst Type. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1046,7 +1046,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TM</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Test Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1060,7 +1060,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_DLL_RESET</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DLL Reset. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1074,7 +1074,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_WR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Write Recovery. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg_timing consumer: various @@ -1087,7 +1087,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_DLL_PPD</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DLL Precharge PD. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1101,7 +1101,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_DLL_ENABLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DLL Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1115,7 +1115,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TDQS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>TDQS. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1129,7 +1129,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_WR_LVL_ENABLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Write Level Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1143,7 +1143,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_OUTPUT_BUFFER</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DRAM Qoff. Enables or disables DRAM output. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1157,7 +1157,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_PASR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Partial Array Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1171,7 +1171,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_ASR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Auto Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1185,7 +1185,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_SRT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Self-Refresh Temperature Range. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1199,7 +1199,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_MPR_LOC</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Multi Purpose Register Location. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1212,7 +1212,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_MPR_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Multi Purpose Register Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -1226,7 +1226,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_RCD_CNTL_WORD_0_15</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RCD Control Word. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1241,7 +1241,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_EFF_DIMM_RCD_CNTL_WORD_X</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Additional RCD Control Word for DDR4. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1256,7 +1256,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC00</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled. For DIMM vendor test purpose, output inversion can be disabled. When disabled, register tPDM is not guaranteed to be met. NOTE: creator: mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8. 00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on. @@ -1273,7 +1273,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC01</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode. creator: mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg @@ -1288,7 +1288,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC02</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC02: Timing and IBT Control Word; mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1302,7 +1302,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC03</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC03 - CA and CS Signals Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1316,7 +1316,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC04</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1330,7 +1330,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC05</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC05 - Clock Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1344,7 +1344,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC06_07</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC06: Command Space Control Word definition; mss_eff_cnfg will set Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM creator: mss_eff_cnfg consumer: mss_dram_init @@ -1358,7 +1358,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC08</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC08: Input/Output Configuration Control Word; mss_eff_cnfg will set Default value - 0x03. Values Range from 00 to 08 decimal. Check the stack height and calculate dynamically; 00 = Stack height_8; 01 = Stack height_4; 02 = Stack height_2; creator: mss_eff_cnfg @@ -1373,7 +1373,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC09</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC06: Command Space Control Word definition;mss_eff_cnfg will set Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1387,7 +1387,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC10</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RDIMM Operating Speed; Read from ATTR_CEN_MSS_FREQ; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1401,7 +1401,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC11</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_CEN_MSS_VOLT.mss_eff_cnfg will set Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1415,7 +1415,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC12</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC0C - Training Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1429,7 +1429,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC13</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC0D - DIMM Configuration Control Word; mss_eff_cnfg will set Default value - 0B. Values Range from 00 to 15 decimal. Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc); creator: mss_eff_cnfg consumer: mss_dram_init @@ -1443,7 +1443,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC14</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC0E - Parity Control Word; mss_eff_cnfg will set Default value - 00. Check from ATTR_CEN_EFF_CA_PARITY and assign; Values Range from 00 to 0F. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1457,7 +1457,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC15</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC0F - Command Latency Adder Control Word; mss_eff_cnfg will set Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1471,7 +1471,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_1x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC1x - Internal VrefCA Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1485,7 +1485,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_2x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC2x: I2C Bus Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1499,7 +1499,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_3x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC3x - Fine Granularity RDIMM Operating Speed; mss_eff_cnfg will set Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1513,7 +1513,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_4x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC4x: CW Source Selection Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1527,7 +1527,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_5x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1541,7 +1541,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_6x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC6x: CW Data Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1555,7 +1555,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_7x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC7x: IBT Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1569,7 +1569,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_8x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1583,7 +1583,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_9x</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RC9x1: QxODT[1:0] Write Pattern Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1597,7 +1597,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_Ax</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RCAx1: QxODT[1:0] Read Pattern Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1611,7 +1611,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DIMM_DDR4_RC_Bx</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>F0RCBx: IBT and MRS Snoop Control Word; mss_eff_cnfg will set Default value - 07. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1626,7 +1626,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_EFF_DIMM_RCD_IBT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1643,7 +1643,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_EFF_DIMM_RCD_MIRROR_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: mss_dram_init @@ -1659,7 +1659,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo mode to use during draminit_train_adv.</description> <valueType>uint8</valueType> <enum>FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8</enum> @@ -1670,7 +1670,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_ADDR_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo mode to use during draminit_train_adv</description> <valueType>uint8</valueType> <enum>FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3</enum> @@ -1681,7 +1681,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_TEST_VALID</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo test to run during draminit_train_adv. Bit wise.</description> <valueType>uint8</valueType> <enum> NONE = 0x00, @@ -1697,7 +1697,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_PARAM_VALID</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo parameters to use during draminit_train_adv. Bit wise.</description> <valueType>uint8</valueType> <enum> PARAM_NONE = 0x00, @@ -1714,7 +1714,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> <valueType>uint8</valueType> <writeable/> @@ -1724,7 +1724,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> <valueType>uint8</valueType> <writeable/> @@ -1734,7 +1734,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> <valueType>uint8</valueType> <writeable/> @@ -1744,7 +1744,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> <valueType>uint8</valueType> <writeable/> @@ -1754,7 +1754,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> <valueType>uint8</valueType> <writeable/> @@ -1764,7 +1764,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_MEMCAL_INTERVAL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the memcal interval in clocks.</description> <valueType>uint32</valueType> <enum>DISABLE = 0</enum> @@ -1775,7 +1775,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_ZQCAL_INTERVAL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the zqcal interval in clocks.</description> <valueType>uint32</valueType> <enum>DISABLE = 0</enum> @@ -1786,7 +1786,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_IBM_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the memory topology type. See centaur workbook.</description> <valueType>uint8</valueType> <enum>UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26</enum> @@ -1798,7 +1798,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_NUM_DROPS_PER_PORT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the number of DIMM dimensions that are valid per port. </description> <valueType>uint8</valueType> <enum>EMPTY = 0, SINGLE = 1, DUAL = 2</enum> @@ -1809,7 +1809,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_STACK_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the DRAM package type.</description> <valueType>uint8</valueType> <enum>NONE = 0, DDP_QDP = 1, STACK_3DS = 2</enum> @@ -1821,7 +1821,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_NUM_MASTER_RANKS_PER_DIMM</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the number of master ranks per DIMM.</description> <valueType>uint8</valueType> <writeable/> @@ -1832,7 +1832,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_NUM_PACKAGES_PER_RANK</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the number of DRAM packages per rank.</description> <valueType>uint8</valueType> <writeable/> @@ -1843,7 +1843,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_NUM_DIES_PER_PACKAGE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Specifies the number of DRAM dies per package.</description> <valueType>uint8</valueType> <writeable/> @@ -1854,7 +1854,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>This is the throttle numerator setting for cfg_nm_n_per_mba creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description> <valueType>uint32</valueType> <writeable/> @@ -1865,7 +1865,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_MEM_THROTTLE_DENOMINATOR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>This is the throttle denominator setting for cfg_nm_m creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description> <valueType>uint32</valueType> <writeable/> @@ -1876,7 +1876,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>This is the throttle numerator setting for cfg_nm_n_per_chip creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description> <valueType>uint32</valueType> <writeable/> @@ -1887,7 +1887,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_MEM_WATT_TARGET</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Total memory power limit in cW for the dimms on the memory channel pair. Used to compute the throttles on the channel and/or dimms creator: unknown consumer: mss_eff_config firmware notes: none</description> <valueType>uint32</valueType> <writeable/> @@ -1898,7 +1898,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_POWER_SLOPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Master Power slope value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1910,7 +1910,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_POWER_SLOPE2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Supplier Power slope value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1922,7 +1922,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_POWER_INT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Master Power intercept value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1934,7 +1934,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_POWER_INT2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Supplier Power intercept value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1946,7 +1946,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_TOTAL_POWER_SLOPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Master Total Power slope value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1958,7 +1958,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_TOTAL_POWER_SLOPE2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Supplier Total Power slope value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1970,7 +1970,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_TOTAL_POWER_INT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Master Total Power intercept value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1982,7 +1982,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_TOTAL_POWER_INT2</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Supplier Total Power intercept value for dimm</description> <valueType>uint32</valueType> <writeable/> @@ -1995,7 +1995,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_MSS_DIMM_MAXBANDWIDTH_GBS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DIMM Max Bandwidth in GBs output from thermal procedures</description> <valueType>uint32</valueType> <writeable/> @@ -2009,7 +2009,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_MSS_DIMM_MAXBANDWIDTH_MRS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DIMM Max Bandwidth in MRs output from thermal procedures</description> <valueType>uint32</valueType> <writeable/> @@ -2023,7 +2023,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Channel Pair Max Bandwidth in GBs output from thermal procedures</description> <valueType>uint32</valueType> <writeable/> @@ -2036,7 +2036,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Channel Pair Max Bandwidth MRs output from thermal procedures</description> <valueType>uint32</valueType> <writeable/> @@ -2049,7 +2049,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_MSS_DIMM_MAXPOWER</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DIMM Max Power output from thermal procedures</description> <valueType>uint32</valueType> <writeable/> @@ -2062,7 +2062,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_CHANNEL_PAIR_MAXPOWER</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Channel Pair Max Power output from thermal procedures</description> <valueType>uint32</valueType> <writeable/> @@ -2072,7 +2072,7 @@ firmware notes: none</description> </attribute> <attribute> <id>ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Runtime throttle numerator setting for cfg_nm_n_per_mba</description> <valueType>uint32</valueType> <writeable/> @@ -2083,7 +2083,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Runtime throttle denominator setting for cfg_nm_m</description> <valueType>uint32</valueType> <writeable/> @@ -2094,7 +2094,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Runtime throttle numerator setting for cfg_nm_n_per_chip</description> <valueType>uint32</valueType> <writeable/> @@ -2266,7 +2266,7 @@ Measured in GB</description> --> <attribute> <id>ATTR_CEN_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>A bit vector (per Dean's request) specifying if a DIMM is functional. DIMM attributes, such as SIZE, are qualified by this bit vector. The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional. 0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional. A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none This factors in functionality</description> <valueType>uint8</valueType> @@ -2278,7 +2278,7 @@ This factors in functionality</description> <attribute> <id>ATTR_CEN_EFF_DRAM_LPASR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description> Low Power Auto Self-Refresh. This is for DDR4 MRS2. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2292,7 +2292,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_MPR_PAGE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>MPR Page Selection This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2306,7 +2306,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_GEARDOWN_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2320,7 +2320,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_PER_DRAM_ACCESS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Per DRAM accessibility. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2333,7 +2333,7 @@ firmware notes: none</description> </attribute> <attribute> <id>ATTR_CEN_EFF_TEMP_READOUT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Temperature sensor readout. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2347,7 +2347,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_FINE_REFRESH_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Fine refresh mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2361,7 +2361,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_CRC_WR_LATENCY</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>write latency for CRC and DM. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2375,7 +2375,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_MPR_RD_FORMAT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>MPR READ FORMAT. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2389,7 +2389,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_MAX_POWERDOWN_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Max Power down mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2403,7 +2403,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_TEMP_REF_RANGE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Temp ref range. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2417,7 +2417,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_TEMP_REF_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Temp controlled ref mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2431,7 +2431,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_INT_VREF_MON</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Internal Vref Monitor.. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2445,7 +2445,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_CS_CMD_LATENCY</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2459,7 +2459,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_SELF_REF_ABORT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Self Refresh Abort. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2473,7 +2473,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_RD_PREAMBLE_TRAIN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Read Pre amble Training Mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2487,7 +2487,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_RD_PREAMBLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Read Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2501,7 +2501,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_WR_PREAMBLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Write Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2515,7 +2515,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_CA_PARITY_LATENCY</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2529,7 +2529,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_CRC_ERROR_CLEAR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>CRC Error Clear. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2543,7 +2543,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_CA_PARITY_ERROR_STATUS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>C/A Parity Error Status. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2557,7 +2557,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_ODT_INPUT_BUFF</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>ODT Input Buffer during power down. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2572,7 +2572,7 @@ firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_EFF_RTT_PARK</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RTT_Park value. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2588,7 +2588,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_CA_PARITY</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>CA Parity Persistance Error. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2602,7 +2602,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DATA_MASK</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Data Mask. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2616,7 +2616,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_WRITE_DBI</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Write DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2630,7 +2630,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_READ_DBI</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Read DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various @@ -2644,7 +2644,7 @@ firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various @@ -2658,7 +2658,7 @@ Firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_VREF_DQ_TRAIN_RANGE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various @@ -2673,7 +2673,7 @@ Firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>vrefdq_train enable. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various @@ -2688,7 +2688,7 @@ Firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_DRAM_TCCD_L</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various @@ -2703,7 +2703,7 @@ Firmware notes: none</description> <!-- <attribute> <id>ATTR_CEN_EFF_DRAM_TCCD_S</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>tccd_S. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various @@ -2718,7 +2718,7 @@ Firmware notes: none</description> <attribute> <id>ATTR_CEN_TCCD_L</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various @@ -2732,7 +2732,7 @@ Firmware notes: none</description> <attribute> <id>ATTR_CEN_EFF_WRITE_CRC</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Write CRC control for DDR4 in MRS2. Set in mss_eff_cnfg. Each memory channel will have a value. Creator: mss_eff_cnfg Consumer:various @@ -2746,7 +2746,7 @@ Firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_CAL_STEP_ENABLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL [1] WR_LEVEL [2] DQS_ALIGN @@ -2790,7 +2790,7 @@ bits6:7 will be consumed together to form COARSE_LVL. </description> <attribute> <id>ATTR_CEN_MSS_SLEW_RATE_DATA</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances. The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms. The 3rd dimension is the rate: 3,4,5 or 6 V/ns. Computed and sent to the correct data blocks in phy_reset. Also used in advanced training</description> <valueType>uint8</valueType> <writeable/> @@ -2801,7 +2801,7 @@ bits6:7 will be consumed together to form COARSE_LVL. </description> <attribute> <id>ATTR_CEN_MSS_SLEW_RATE_ADR</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances. The first dimension is the port. The second is the impedance of 15, 20, 30 and 40 Ohms. The 3rd dimension is the rate:3, 4,5 or 6 V/ns. Computed and sent to the correct data blocks in phy_reset. Also used in advanced training</description> <valueType>uint8</valueType> <writeable/> @@ -2825,7 +2825,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MSS_ALLOW_SINGLE_PORT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes. Used in eff_config</description> <valueType>uint8</valueType> <enum>FALSE = 0, TRUE = 1</enum> @@ -2836,7 +2836,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MSS_DQS_SWIZZLE_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1, type 2 is for Pallmeto. Additional types maybe defined if new boards have even different DQS swizzle features</description> <valueType>uint8</valueType> <enum>NORMAL_TYPE_0 = 0, GLACIER_TYPE_1 = 1, ISDIMM_TYPE_2 = 2</enum> @@ -2874,7 +2874,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MCBIST_PATTERN</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables mcbist data pattern selection.</description> <valueType>uint32</valueType> <writeable/> @@ -2884,7 +2884,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MCBIST_TEST_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Enables mcbist test type selection.</description> <valueType>uint32</valueType> <writeable/> @@ -2894,7 +2894,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MCBIST_PRINTING_DISABLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>MCBIST support for printing</description> <valueType>uint8</valueType> <writeable/> @@ -2904,7 +2904,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MCBIST_DATA_ENABLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>MCBIST support for enabling data</description> <valueType>uint8</valueType> <writeable/> @@ -2914,7 +2914,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MCBIST_USER_RANK</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>MCBIST support for rank selection</description> <valueType>uint8</valueType> <writeable/> @@ -2924,7 +2924,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_MCBIST_USER_BANK</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>MCBIST support for bank selection</description> <valueType>uint8</valueType> <writeable/> @@ -2934,7 +2934,7 @@ Firmware shares some code with the processor, so the attribute is named so they <attribute> <id>ATTR_CEN_SCHMOO_MULTIPLE_SETUP_CALL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>MCBIST for multiple setup</description> <valueType>uint8</valueType> <writeable/> @@ -2945,7 +2945,7 @@ Firmware shares some code with the processor, so the attribute is named so they <!-- <attribute> <id>ATTR_CEN_EFF_BUFFER_LATENCY</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Additional buffer latency in the case of RDIMMs and LRDIMMs. It is expected that this value will come from the VPD</description> <valueType>uint8</valueType> <platInit/> @@ -2958,7 +2958,7 @@ Firmware shares some code with the processor, so the attribute is named so they <!-- <attribute> <id>ATTR_CEN_EFF_LRDIMM_WORD_X</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Additional buffer control word for LRDIMM building of the BCW</description> <valueType>uint64</valueType> <platInit/> @@ -2972,7 +2972,7 @@ Firmware shares some code with the processor, so the attribute is named so they <!-- <attribute> <id>ATTR_CEN_LRDIMM_MR12_REG</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>LRDIMM MR1,2 register. DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks. Eff config should set this up.</description> <valueType>uint8</valueType> @@ -2986,7 +2986,7 @@ DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance <!-- <attribute> <id>ATTR_CEN_EFF_LRDIMM_ADDITIONAL_CNTL_WORDS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>LRDIMM additional RCD control words as set by DIMM SPD: F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11, F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15. @@ -3002,7 +3002,7 @@ Eff config should set this up</description> <!-- <attribute> <id>ATTR_CEN_LRDIMM_ADDITIONAL_CNTL_WORDS</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>LRDIMM additional RCD control words as set by DIMM SPD: F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11, F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15. @@ -3017,7 +3017,7 @@ Eff config should set this up</description> <attribute> <id>ATTR_CEN_LRDIMM_RANK_MULT_MODE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>LRDIMM rank multiplication mode. Will be set at an MBA level with one policy to be used</description> <valueType>uint8</valueType> @@ -3029,7 +3029,7 @@ Will be set at an MBA level with one policy to be used</description> <attribute> <id>ATTR_CEN_MSS_THROTTLE_CONTROL_RAS_WEIGHT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>RAS weight to use for memory throttle control - set in thermal procedures</description> <valueType>uint8</valueType> <writeable/> @@ -3039,7 +3039,7 @@ Will be set at an MBA level with one policy to be used</description> <attribute> <id>ATTR_CEN_MSS_THROTTLE_CONTROL_CAS_WEIGHT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>CAS weight to use for memory throttle control - set in thermal procedures</description> <valueType>uint8</valueType> <writeable/> @@ -3049,7 +3049,7 @@ Will be set at an MBA level with one policy to be used</description> <attribute> <id>ATTR_CEN_MCBIST_RANDOM_SEED_VALUE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> <valueType>uint32</valueType> <writeable/> @@ -3059,7 +3059,7 @@ Will be set at an MBA level with one policy to be used</description> <attribute> <id>ATTR_CEN_MCBIST_RANDOM_SEED_TYPE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> <valueType>uint8</valueType> <writeable/> @@ -3070,7 +3070,7 @@ Will be set at an MBA level with one policy to be used</description> <!-- <attribute> <id>ATTR_CEN_MCBIST_DDR4_PDA_ENABLE</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description>Controls PDA train enable or PBA. 00 - Disable; 01 - PDA; 02 - PBA(Lrdimm)</description> <valueType>uint8</valueType> <writeable/> @@ -3131,7 +3131,7 @@ Will be set at an MBA level with one policy to be used</description> <attribute> <id>ATTR_CEN_MSS_EFF_VPD_VERSION</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <targetType>TARGET_TYPE_MBA</targetType> <description> The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword </description> diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_generic_shmoo_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_generic_shmoo_errors.xml index ab4536c68..e84b96714 100644 --- a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_generic_shmoo_errors.xml +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_generic_shmoo_errors.xml @@ -43,7 +43,7 @@ </description> <callout> <childTargets> - <parent>MBA_CHIPLET</parent> + <parent>MBA_TARGET</parent> <childType>TARGET_TYPE_DIMM</childType> <childPort>MBA_PORT_NUMBER</childPort> <childNumber>MBA_DIMM_NUMBER</childNumber> @@ -52,7 +52,7 @@ </callout> <deconfigure> <childTargets> - <parent>MBA_CHIPLET</parent> + <parent>MBA_TARGET</parent> <childType>TARGET_TYPE_DIMM</childType> <childPort>MBA_PORT_NUMBER</childPort> <childNumber>MBA_DIMM_NUMBER</childNumber> diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_mcbist_common_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_mcbist_common_errors.xml index 382a752a5..a545e1d4d 100644 --- a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_mcbist_common_errors.xml +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_mcbist_common_errors.xml @@ -40,14 +40,14 @@ <rc>RC_CEN_MSS_MCBIST_TIMEOUT_ERROR</rc> <description>Timeout on MCBIST configuration register polling.</description> <callout> - <target>MBA_CHIPLET</target> + <target>MBA_TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>MBA_CHIPLET</target> + <target>MBA_TARGET</target> </deconfigure> <gard> - <target>MBA_CHIPLET</target> + <target>MBA_TARGET</target> </gard> </hwpError> </hwpErrors> |
