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author | Luke Mulkey <lwmulkey@us.ibm.com> | 2017-03-15 13:30:27 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-04 10:52:47 -0400 |
commit | c2b56cd511ff96c43a9fd67a8c1201842ab024ac (patch) | |
tree | bfb2dea9f493c5ce8e7da6cc4bf24e4733afc97c /src/import/chips/centaur/procedures/xml | |
parent | c9f1ae5a28dd6d5e53b9f59823befe465856d706 (diff) | |
download | talos-hostboot-c2b56cd511ff96c43a9fd67a8c1201842ab024ac.tar.gz talos-hostboot-c2b56cd511ff96c43a9fd67a8c1201842ab024ac.zip |
p9c_mss_draminit_training
Change-Id: I2427148addbadcd09f77d81e49acae10ccbbd0d3
Original-Change-Id: Ibecdb6ad71eb8143440d09c5c69c3edfc398f97f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38069
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43779
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures/xml')
-rw-r--r-- | src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml | 342 |
1 files changed, 342 insertions, 0 deletions
diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml new file mode 100644 index 000000000..06648afb4 --- /dev/null +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml @@ -0,0 +1,342 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> + +<!-- --> +<!-- @file p9c_memory_mss_draminit_training_errors.xml --> +<!-- @brief Error xml for draminit training --> +<!-- --> +<!-- *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> --> +<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> --> +<!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> --> +<!-- *HWP Team: Memory --> +<!-- *HWP Level: 1 --> +<!-- *HWP Consumed by: FSP:HB --> +<!-- --> + +<hwpErrors> +<registerFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3</scomRegister> + <scomRegister>CEN_MBA_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4</scomRegister> +</registerFfdc> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_SETBBM</rc> + <description>Unknown Value for DRAM_WIDTH being used.</description> + <ffdc>WIDTH</ffdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET_MBA_ERROR</target> + </deconfigure> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_GETBBM</rc> + <description>Unknown Value for DRAM_WIDTH being used.</description> + <ffdc>WIDTH</ffdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET_MBA_ERROR</target> + </deconfigure> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR</rc> + <description>Unknown Value for DIMM_SPARE being used.</description> + <ffdc>PORT</ffdc> + <ffdc>DIMM</ffdc> + <ffdc>RANK</ffdc> + <ffdc>SPARE</ffdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET_MBA_ERROR</target> + </deconfigure> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_C4_PHY_TRANSLATION_ERROR</rc> + <description>Incorrect translation of bad bit mask between C4 and PHY</description> + <ffdc>PORT</ffdc> + <ffdc>BLOCK</ffdc> + <ffdc>QUAD</ffdc> + <ffdc>PHYLANE</ffdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA_ERROR</target> + </deconfigure> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR</rc> + <description>Write Leveling has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR</rc> + <description>DQS Alignment has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR</rc> + <description>Read CLK to SYS CLK Alignment has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR</rc> + <description>Read Centering has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR</rc> + <description>Write centering has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_COURSE_RD_CENTERING_ERROR</rc> + <description>Course Read Centering has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_CENTERING_ERROR</rc> + <description>Custom Pattern Read Centering has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_CENTERING_ERROR</rc> + <description>Custom Pattern Write Centering has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR</rc> + <description>Digital Eye has returned a fail for a given position within this calibration.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id> + <target>TARGET_MBA_ERROR</target> + <targetType>TARGET_TYPE_MBA</targetType> + </collectRegisterFfdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +</hwpErrors> |