mss_get_ecid code for 11/15 SOA chkpt

Change-Id: I25a2e713e357b57f6f6bf63db0b6a2b7c45cc726
Original-Change-Id: I1c61f1f20fcdd16d014d13833f3a8eef92559175
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32617
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Johannes Koesters <koesters@de.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44089
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 455 insertions, 3 deletions

diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml
index e7a913b48..3f02a191d 100644
--- a/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml
+++ b/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml
@@ -23,8 +23,8 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
-  <!-- ********************************************************************* -->
-  <attribute>
+<!-- ********************************************************************* -->
+ <attribute>
     <id>ATTR_CEN_EC_FEATURE_SWITCH_DIV24_RUN_MODE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>
@@ -59,5 +59,457 @@
       </chip>
     </chipEcFeature>
   </attribute>
-  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, it sets stop on error for xtsop in the Centaur arrays using ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_SAFE_MODE_THROTTLE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, it sets Safe mode throttles using sys attributes  ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP and ATTR_CEN_MRW_MEM_THROTTLE_DENOMINATOR.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, it allow RCE to be reported even if we also have chip marks or symbol marks in place. MBSTR(60)=1 and MBSECC(16)=1, DD2 is set.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_PAGE_MODE_FOR_RRQ</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, it allows super fast read to go faster. MBA_RRQ0Q(57) cfg_rrq_opp_page_mode_en RW DD2 is set.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_TRACE_LCL_CLK_GATE_CTRL</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  For HW259719. If true, Trace LCL_CLK_GATE_CTRL will be enabled.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_NM_CHANGE_AFTER_SYNC</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  IF TRUE, ENABLE NM change after sync.
+        This fix that is going into DD2 (to use values in N/M shadow registers when a sync command is seen), we should be able to change M to a different value if we wanted to without any issues.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_ROW_HAMMER_FEATURE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  IF TRUE, Enable ROW HAMMER ENHANCEMENT FOR DD2.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_WRITE_FIR_MASK_FEATURE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      Returns true if the chip needs to fix the fir_mask register in the DDRPHY.  This is for HW217419.
+	True if: Centaur EC 10
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_BLUEWATERFALL_NWELL_BROKEN_CHECK_FLAG</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD1.0 (TRUE), otherwise FALSE.  If true, subversion will be checked in mss_get_cen_ecid.C to determine if changes need to be made to the transistor misplaced in the nwell.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will continue with processing other DP18 blocks, if one fails.  In DD2, this attribute must be set to false so that the failing hardware (centaur) is marked as bad and not the DIMM.  Set by firwmare using the EC level or by a MRW
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_MSS_READ_PHASE_SELECT_RESET</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      If true, then training and periodic training needs to make adjustments to the read phase select.
+      In DD2, this is expected to be fixed.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_CHECK_L4_CACHE_ENABLE_UNKNOWN</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      If true then mss_get_cen_ecid needs to read an ECBIT from the ECID in
+      order to determine if the L4 Cache Enable data in the ECID is in an
+      unknown state.
+      This is true for Centaur 1.*
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_EC_FEATURE_DISABLE1_REG_FIXED</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If false, then draminit_training will also set the wrclk registers to disable appropriate dqs based on the bad bit map attribute and the swizzle(board dependent).  If true, draminit_training will just do the default disable0 and disable1 registers.</description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+</attribute>
+
+<attribute>
+    <id>ATTR_CEN_MSS_EC_FEATURE_DISABLE1_RDCLK_REG_FIXED</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If false, then draminit_training will also set the rdclk registers to disable appropriate dqs based on the bad bit map attribute and the swizzle(board dependent).  If true, draminit_training will just do the default disable0 and disable1 registers.</description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+</attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ECID_CONTAINS_PORT_LOGIC_BAD_INDICATION</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      If true then mss_get_cen_ecid reads the ECID bits to determine if
+      logic on either of the ports are good.  For DD2, these bits are not
+      used for this purpose and so the check is not made.
+      This is true for Centaur 1.*
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_MCBIST_RANDOM_DATA_GEN</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.   If false, this will enable the  power bus ECC and FIFO mode workarounds of DD1.x for Random Data .
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_MCBIST_TRAP_RESET</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, work around for error trap reset logic which  clears  trap registers will be enabled.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_MCBIST_RANDOM_ADDRESS</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.   If false, this will enable workaround for start and end counters for Random Addressing.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+    <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_SCOM_PARITY_ERROR_HW244827_FIXED</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If false, draminit_mc will execute a putscom to clear the scom parity error fir for all densities on DD1.X parts.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+    <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, MBSPA bit 8 is masked, and MBSPA bit 0 is unmasked and configured to report when maint cmd either stops clean or stops on error. Otherwise, MBSPA bit 0 is masked, and MBSPA bit 8 is unmasked. NOTE: For DD1 when using MBSPA bit 8, a scan init is needed to enable the WAT workaround allows bit 8 to report when maint cmd either stops clean or stops on error. The scan init is enabled for DD1 and disabled for DD2, but does not use this same attribute.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_USE_FIRST_SUPPLIER_FOR_INVALID_MODULE_ID</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        The getMBvpdSlopeInterceptData Attribute Accessor returns power data from the MW (master) and MV (supplier) Centaur DIMM VPD.
+        For MV attributes, the Attribute Accessor finds the Manufacturer-ID from JEDEC SPD (#I) and then matches it to a Supplier-ID in the array of supplier entries in the MV field .
+        For Centaur DD 1.X chips, the Manufacturer-ID may be invalid.
+The getMBvpdSlopeInterceptData Attribute Accessor, if it does not find a matching Supplier-ID in MV, will  return the data for the first supplier on Centaur DD 1.X chips.
+       This is true for Centaur 1.*
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_SAFEMODE_THROTTLE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.   If true, this will enable safe mode throttle values to be set during the IPL in mss_thermal_init.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+    <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_DD2_FIR_BIT_DEFN_CHANGES</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, mss_unmask_errors.C will use the DD2 FIR bit definitions when setting FIR action regs and masks.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+      <id>ATTR_CEN_CENTAUR_EC_FEATURE_RDCLK_PR_UPDATE_HW236658_FIXED</id>
+      <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+      <description>
+         Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If false, draminit_mc will execute a putscom to set bit 52 (PER_RDCLK_UPDATE_DISABLE) of DP18 Read Diag Cfg 5 on DD1.X parts.
+      </description>
+      <chipEcFeature>
+        <chip>
+          <name>ENUM_ATTR_NAME_CENTAUR</name>
+          <ec>
+            <value>0x20</value>
+            <test>GREATER_THAN_OR_EQUAL</test>
+          </ec>
+        </chip>
+       </chipEcFeature>
+   </attribute>
+
+    <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_DD2_ENABLE_EXIT_POINT_1</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If true, exit point 1 will be enabled if any mark in markstore.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CEN_CENTAUR_EC_FEATURE_DISABLE_VDDR_DYNAMIC_VID</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on EC less than DD2.0 (TRUE), otherwise FALSE.   If true, mss_volt_vddr_offset will use the value from mss_volt instead of the calculated dynamic vid value, even if vddr dynamic vid is enabled in the MRW.  Centaur DD1.X chips need vmem voltage to be at 1.35V.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+
 </attributes>