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| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-02-28 15:58:55 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-16 13:39:44 -0400 |
| commit | 013207df79b31b32891ba9f16ef244e2dbd3da1a (patch) | |
| tree | bb9487d00650c9e33fcdfdf397e3b7433dc70919 /src/import/chips/centaur/procedures/xml/attribute_info | |
| parent | 18d91f4a458f0afb827be3495fda496543711a62 (diff) | |
| download | talos-hostboot-013207df79b31b32891ba9f16ef244e2dbd3da1a.tar.gz talos-hostboot-013207df79b31b32891ba9f16ef244e2dbd3da1a.zip | |
Updates p9c SPD read to include DDR3
Change-Id: I9ecb60715f4b6ef88b475891a8779cab4102c52b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54889
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54903
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures/xml/attribute_info')
| -rw-r--r-- | src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml | 26 |
1 files changed, 5 insertions, 21 deletions
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml index 9088d49be..008109f23 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml @@ -228,30 +228,14 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Platform support must call an Accessor HWP. For DDR3, the values would be from CL_4 through CL_18 For DDR4, the values would be from CL_7 through CL_24 + Note: the attributes decode changes from DDR3 to DDR4 + In DDR3, we index from the lowest CL: CL_4 + In DDR4, we index from the lowest CL: CL_7 </description> <valueType>uint32</valueType> <enum> - CL_24 = 0x00100000, - CL_23 = 0x00080000, - CL_22 = 0x00040000, - CL_21 = 0x00020000, - CL_20 = 0x00010000, - CL_19 = 0x00008000, - CL_18 = 0x00004000, - CL_17 = 0x00002000, - CL_16 = 0x00001000, - CL_15 = 0x00000800, - CL_14 = 0x00000400, - CL_13 = 0x00000200, - CL_12 = 0x00000100, - CL_11 = 0x00000080, - CL_10 = 0x00000040, - CL_9 = 0x00000020, - CL_8 = 0x00000010, - CL_7 = 0x00000008, - CL_6 = 0x00000004, - CL_5 = 0x00000002, - CL_4 = 0x00000001 + DDR3_LOWEST_CL = 4, + DDR4_LOWEST_CL = 7 </enum> <writeable/> </attribute> |
