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author | Louis Stermole <stermole@us.ibm.com> | 2018-06-06 13:13:09 -0500 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-07-27 10:12:05 -0500 |
commit | 85a561df01c8237bdaa48c62871b2cf0101abbbc (patch) | |
tree | 26cc90b9b3524515bd951414e322583c7d671c56 /src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml | |
parent | 832ce225929113e43bafee2ed300f56dc026301c (diff) | |
download | talos-hostboot-85a561df01c8237bdaa48c62871b2cf0101abbbc.tar.gz talos-hostboot-85a561df01c8237bdaa48c62871b2cf0101abbbc.zip |
Improve WR_VREF shmoo algorithm in p9c training_adv
Change-Id: I0f07072b4e5e078c8ea3845abbf8933a03a8bf62
CQ:SW439234
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/60047
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/60056
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Disable-CI: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml')
-rw-r--r-- | src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index 77b49ddaa..d532c13e9 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -121,11 +121,11 @@ Set by: PLL settings written by Dave Cadigan</description> <attribute> <id>ATTR_CEN_MSS_VREF_CAL_CNTL</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; 0x03=Box shmoo; + <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=P8_DRAM - Enable V-Ref Train DRAM Level (P8 algorithm); 0x02=P8_RANK Level Training (P8 algorithm); 0x03=Box shmoo; 0x04=Ternary shmoo Default Value = 0x03 for box shmoo on all platforms </description> <valueType>uint8</valueType> - <enum>DISABLE = 0, DRAM = 1, RANK = 2, BOX = 3</enum> + <enum>DISABLE = 0, P8_DRAM = 1, P8_RANK = 2, BOX = 3, TERNARY = 4</enum> <default>3</default> <platInit/> <odmVisable/> @@ -133,6 +133,20 @@ Set by: PLL settings written by Dave Cadigan</description> <persistRuntime/> </attribute> +<attribute> +<id>ATTR_CEN_MSS_VREF_CAL_DELTA_FROM_NOMINAL</id> + <targetType>TARGET_TYPE_MBA</targetType> + <description>Controls search boundaries for WR_VREF Ternary shmoo. Value is a delta of register ticks from nominal + Default Value = 0x08 (taken from characterization values), Max value = 0x19 +</description> + <valueType>uint8</valueType> + <default>0x08</default> + <platInit/> + <odmVisable/> + <odmChangeable/> + <persistRuntime/> +</attribute> + <!-- <attribute> <id>ATTR_CEN_MSS_DIMM_MFG_ID_CODE</id> |