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author | Louis Stermole <stermole@us.ibm.com> | 2018-10-18 19:01:53 -0500 |
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committer | Christian R Geddes <crgeddes@us.ibm.com> | 2018-10-23 16:26:01 -0500 |
commit | fecb93f473161bae5bded405aaca525c78f80a22 (patch) | |
tree | 576c0a2d1cb976693e3e5a717160f2a2dafcfd0a /src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H | |
parent | a45ace1ec733a7a3f17988715a43e06c1cc414f5 (diff) | |
download | talos-hostboot-fecb93f473161bae5bded405aaca525c78f80a22.tar.gz talos-hostboot-fecb93f473161bae5bded405aaca525c78f80a22.zip |
Fix Centaur workaround in p9c_mss_row_repair
When a given DRAM position is marked bad on all configured ranks
in the VPD the row repair should be skipped and the entry in
ATTR_ROW_REPAIR_DATA should be cleared
Change-Id: Iedfc856041c7814e25925ddcc9a81855c5249657
CQ:SW448925
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67739
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67741
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H')
-rw-r--r-- | src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H index 22fe5b5b2..37e26275e 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.H @@ -84,6 +84,19 @@ extern "C" /// @return FAPI2_RC_SUCCESS iff successful fapi2::ReturnCode p9c_mss_deploy_row_repairs(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba); + /// @brief Check the bad bits data to see if a DRAM was not calibrated + /// @param[in] i_dram_width the DRAM width + /// @param[in] i_dram the DRAM index + /// @param[in] i_rankpair_table table of rank to rank pairs for this port + /// @param[in] i_bad_bits array bad bits data from VPD for all ranks on the port + /// @param[out] o_uncalibrated true if DRAM was marked bad in all ranks, false otherwise + /// @return FAPI2_RC_SUCCESS iff successful + fapi2::ReturnCode check_for_uncalibrated_dram(const uint8_t i_dram_width, + const uint8_t i_dram, + const uint8_t (&i_rankpair_table)[MAX_RANKS_PER_PORT], + const uint8_t (&i_bad_bits)[MAX_RANKS_PER_PORT][DIMM_DQ_RANK_BITMAP_SIZE], + bool& o_uncalibrated); + /// @brief Clear the corresponding bad_bits after a row repair operation /// @param[in] i_dram_width the DRAM width /// @param[in] i_dram the DRAM index @@ -120,13 +133,11 @@ extern "C" /// @param[in] i_dram_width the DRAM width /// @param[in] i_row_repair_data array of row repair attribute values for the DIMM /// @param[out] o_repairs_per_dimm array of row repair data buffers - /// @param[in,out] io_dram_bad_in_ranks array of how many ranks in which each DRAM was found to need a repair /// @return FAPI2_RC_SUCCESS iff successful fapi2::ReturnCode build_row_repair_table(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint8_t i_dram_width, const uint8_t i_row_repair_data[MAX_RANKS_PER_DIMM][ROW_REPAIR_BYTES_PER_RANK], - std::vector<fapi2::buffer<uint32_t>>& o_repairs_per_dimm, - uint8_t io_dram_bad_in_ranks[MC_MAX_DRAMS_PER_RANK_X4]); + std::vector<fapi2::buffer<uint32_t>>& o_repairs_per_dimm); } #endif |