summaryrefslogtreecommitdiffstats
path: root/src/import/chips/centaur/common
diff options
context:
space:
mode:
authorLuke Mulkey <lwmulkey@us.ibm.com>2017-01-04 13:55:33 -0600
committerChristian R. Geddes <crgeddes@us.ibm.com>2017-08-30 23:16:33 -0400
commitbe4329ca37507ac3dfc049d0ba9828e879683e69 (patch)
tree41f19de885c193b72b1eb267c9332ed581490914 /src/import/chips/centaur/common
parentd459810061ec9df769edcfdd2ce31791ca9f89af (diff)
downloadtalos-hostboot-be4329ca37507ac3dfc049d0ba9828e879683e69.tar.gz
talos-hostboot-be4329ca37507ac3dfc049d0ba9828e879683e69.zip
Edit ECID+Perv code to use new gen'd centaur scom headers
RTC 163585 - Done Change-Id: I36c3476d07594382e70772eab050702c80992807 Original-Change-Id: I4fe900e3c1e919ff03158dd4cd02c268667dcbec Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34371 Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44950 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/common')
-rw-r--r--src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H33
1 files changed, 33 insertions, 0 deletions
diff --git a/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H b/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H
index 36a87141f..4d9b572e3 100644
--- a/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H
+++ b/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H
@@ -25,4 +25,37 @@
//Example: To fix an existing definiton
//CEN_FIXREG32 (CEN_MBA_1_CCS_INST_ARR0_10, RULL(0x01234567));
+#include <p9_const_common.H>
+#include <p9_scom_template_consts.H>
+#ifndef CEN_GEN_SCOM_ADDRESSES_FIXES_H
+#define CEN_GEN_SCOM_ADDRESSES_FIXES_H
+REG64( CEN_WRITE_ALL_FUNC_GP3 , RULL(0x6B0F0012), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_WRITE_ALL_FUNC_GP3_AND , RULL(0x6B0F0013), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_WRITE_ALL_FUNC_GP3_OR , RULL(0x6B0F0014), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_WRITE_ALL_PCB_SLAVE_ERRREG , RULL(0x6B0F001F), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_PERV_LOCAL_FIR , RULL(0x0004000A), SH_UNT_PERV , SH_ACS_SCOM_RW );
+REG64( CEN_PERV_TP_LOCAL_FIR , RULL(0x0104000A), SH_UNT_PERV_1 , SH_ACS_SCOM_RW );
+REG64( CEN_PERV_LOCAL_FIR_AND , RULL(0x0004000B), SH_UNT_PERV , SH_ACS_SCOM1_AND );
+REG64( CEN_PERV_TP_LOCAL_FIR_AND , RULL(0x0104000B), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND );
+REG64( CEN_PERV_LOCAL_FIR_OR , RULL(0x0004000C), SH_UNT_PERV , SH_ACS_SCOM2_OR );
+REG64( CEN_PERV_TP_LOCAL_FIR_OR , RULL(0x0104000C), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR );
+REG64( CEN_PERV_LOCAL_FIR_MASK , RULL(0x0004000D), SH_UNT_PERV , SH_ACS_SCOM_RW );
+REG64( CEN_PERV_TP_LOCAL_FIR_MASK , RULL(0x0104000D), SH_UNT_PERV_1 , SH_ACS_SCOM_RW );
+REG64( CEN_PERV_LOCAL_FIR_MASK_AND , RULL(0x0004000E), SH_UNT_PERV , SH_ACS_SCOM1_AND );
+REG64( CEN_PERV_TP_LOCAL_FIR_MASK_AND , RULL(0x0104000E), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND );
+REG64( CEN_PERV_LOCAL_FIR_MASK_OR , RULL(0x0004000F), SH_UNT_PERV , SH_ACS_SCOM2_OR );
+REG64( CEN_PERV_TP_LOCAL_FIR_MASK_OR , RULL(0x0104000F), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR );
+REG64( CEN_GENERIC_GP1 , RULL(0x00000001), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_GP0_AND , RULL(0x00000004), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_GP0_OR , RULL(0x00000005), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_GP3_AND , RULL(0x000F0013), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_GP3_OR , RULL(0x000F0014), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_OPCG_CNTL0 , RULL(0x00030002), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_OPCG_CNTL2 , RULL(0x00030004), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_CLK_REGION , RULL(0x00030006), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_CLK_SCANSEL , RULL(0x00030007), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_CLK_STATUS , RULL(0x00030008), SH_UNT_PERV, SH_ACS_FSI );
+REG64( CEN_GENERIC_CLK_SCANDATA0 , RULL(0x00038000), SH_UNT_PERV, SH_ACS_FSI );
+
+#endif
OpenPOWER on IntegriCloud