Establish a working P9 Hostboot and Simics base

Includes changes for nimbus.por
Making recent Simics usable by Hostboot
Removing portions of code not yet ready
Basic LPC read/write

Change-Id: Ic40a9613934fab7bb6a28a8100685496246bb5ea
RTC:132170
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21931
Tested-by: Jenkins Server
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: Christian Geddes <crgeddes@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

9 files changed, 97 insertions, 90 deletions

diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild
index 7fc9c5842..13ddb092e 100644
--- a/src/build/citest/etc/bbuild
+++ b/src/build/citest/etc/bbuild
@@ -1 +1 @@
-/esw/fips910/Builds/built
+/esw/fips910/Builds/b1116a_1548.910
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 2a0353765..1ca37e54d 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -34,3 +34,17 @@
 #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip
 #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
 
+
+echo "+++ Fixing pnor file in p9_nimbus.simics"
+cp -f $sb/../simics/targets/p9_nimbus/p9_nimbus.simics /tmp/
+cp -f /tmp/p9_nimbus.simics $sb/../simics/targets/p9_nimbus/p9_nimbus.simics
+sed -i '/$image_name =/c\$image_name = "nimbus.pnor"' $sb/../simics/targets/p9_nimbus/p9_nimbus.simics
+
+echo "+++ Patching simicsInfo NIMBUS flash definitions"
+mkdir -p $sb/simu/data
+cp $bbsrc/simu/data/simicsInfo $sb/simu/data/
+sed -i '/^MACHINE:NIMBUS/ s/$/ | IMGS:HOSTBOOT_IMG | IMGS:NIMBUS_IMG/' $sb/simu/data/simicsInfo
+echo "
+IMGS:NIMBUS_IMG | FLASH:nimbus.pnor | LOC:SB_CHAIN/images/ppc/lab/flash" >> \
+    $sb/simu/data/simicsInfo
+
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index 2b1321ffc..af8ace796 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -50,43 +50,11 @@ grep -v "GFW_P8_HB_UNSECURE_OFFSET" \
 echo "SETENV GFW_P8_HB_UNSECURE_OFFSET 58720256" >> \
     $sb/simu/configs/P8_VENICE.config
 
-echo "+++ Patching P9_NIMBUS.config with L3_MB_SIZE."
-egrep -v "GFW_P9_NIMBUS_L3_MB_SIZE|GFW_P9_NIMBUS_HB_BASE_IMG_USE_PNOR|GFW_P9_NIMBUS_HB_BASE_IMG_WITH_ECC" \
-    $BACKING_BUILD/src/simu/configs/P9_NIMBUS.config > \
+echo "+++ Patching P9_NIMBUS.config with extra PARMS"
+cp $bbsrc/simu/configs/P9_NIMBUS.config $sb/simu/configs/
+echo "
+SETENV GFW_P9_NIMBUS_DIMM_CCIN              HABJ
+SETENV GFW_P9_NIMBUS_DIMMS_PER_PROC         16
+SETENV GFW_P9_NIMBUS_DIMM_EC                20
+SETENV GFW_P9_NIMBUS_DIMM_MODEL_EC          0" >> \
     $sb/simu/configs/P9_NIMBUS.config
-echo "SETENV GFW_P9_NIMBUS_L3_MB_SIZE             10
-SETENV GFW_P9_NIMBUS_HB_BASE_IMG_USE_PNOR   no
-SETENV GFW_P9_NIMBUS_HB_BASE_IMG_WITH_ECC   no
-SETENV XSCOM_BASE_ADDR      0x0006010000000000" >> \
-    $sb/simu/configs/P9_NIMBUS.config
-
-echo "+++ Patching simicsInfo with new POWER9 FIPSLEVEL."
-mkdir -p $sb/simu/data
-grep -v "WSALIAS POWER9 FIPSLEVEL" \
-    $BACKING_BUILD/src/simu/data/simicsInfo > \
-    $sb/simu/data/simicsInfo
-echo "WSALIAS POWER9 FIPSLEVEL env/sima/simics-4.8.0/simics-4.8.87/fips/fld36/fi150615g900.48" >> \
-    $sb/simu/data/simicsInfo
-
-echo "+++ Creating p9.act with SBE start action."
-mkdir -p $sb/simu/data/cec-chip
-echo \
-"CAUSE_EFFECT {
-  LABEL=[Master SBE Start Part One - c4t0]
-  WATCH=[STARTSBEREGS(0x0)]
-  CAUSE: TARGET=[STARTSBEREGS(0x0)] OP=[BIT,ON] BIT=[0]
-  EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 0)] OP=[MODULECALL] # jlo_181
-  EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 1)] OP=[MODULECALL] # jlo_181
-  EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 2)] OP=[MODULECALL] # jlo_181
-  EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 3)] OP=[MODULECALL] # jlo_181
-  EFFECT: TARGET=[MODULE(sbeStart, FSIMBOX(0x3A), LOGIC(0xFF0CC004), 0)] OP=[MODULECALL] #dds129
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[0] #Signal Centaur 0 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[1] #Signal Centaur 1 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[2] #Signal Centaur 2 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[3] #Signal Centaur 3 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[4] #Signal Centaur 4 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[5] #Signal Centaur 5 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[6] #Signal Centaur 6 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x1)]  OP=[BIT,ON]  BIT=[7] #Signal Centaur 7 to flush regs
-  EFFECT: TARGET=[STARTSBEREGS(0x0)]  OP=[BIT,OFF] BIT=[0] #reset to 0 so subsequent SBE starts will trigger this action again
-}" > $sb/simu/data/cec-chip/p9.act
diff --git a/src/build/mkrules/dist.targets.mk b/src/build/mkrules/dist.targets.mk
index 196b8d362..06a9a65f5 100644
--- a/src/build/mkrules/dist.targets.mk
+++ b/src/build/mkrules/dist.targets.mk
@@ -36,7 +36,7 @@ ROOTPATH = ../../..
 # The release is created by generating all targets into their subdirectory:
 #    ...release/fsp/...
 #    ...release/vpo/...
-#    ...reelase/tools/...
+#    ...release/tools/...
 #
 
 # Content targets.
@@ -205,6 +205,7 @@ fsp.tar_CONTENTS = \
     img/simics_MURANO_targeting.bin \
     img/simics_VENICE_targeting.bin \
     img/simics_NAPLES_targeting.bin \
+    img/simics_NIMBUS_targeting.bin \
     obj/genfiles/fapiAttrInfo.csv \
     obj/genfiles/fapiAttrEnumInfo.csv \
     obj/genfiles/targAttrInfo.csv \
diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile
index 6c4370b47..d59798ee2 100755
--- a/src/build/mkrules/hbfw/img/makefile
+++ b/src/build/mkrules/hbfw/img/makefile
@@ -240,24 +240,31 @@ ENGD_OBJPATH = ${HBFW_OBJPATH:S/hbfw\/img/engd\/href/g}
 MURANO_TARG_IMG = simics_MURANO_targeting.bin
 NAPLES_TARG_IMG = simics_NAPLES_targeting.bin
 VENICE_TARG_IMG = simics_VENICE_targeting.bin
+NIMBUS_TARG_IMG = simics_NIMBUS_targeting.bin
 MURANO_TARG_IMG_ECC = simics_MURANO_targeting.bin.ecc
 NAPLES_TARG_IMG_ECC = simics_NAPLES_targeting.bin.ecc
 VENICE_TARG_IMG_ECC = simics_VENICE_targeting.bin.ecc
+NIMBUS_TARG_IMG_ECC = simics_NIMBUS_targeting.bin.ecc
 MURANO_SLW_IMG = ${ENGD_OBJPATH:Fs1.ref_image.hdr.bin}
 NAPLES_SLW_IMG = ${ENGD_OBJPATH:Fs1.ref_image.hdr.bin}
 VENICE_SLW_IMG = ${ENGD_OBJPATH:Fp8.ref_image.hdr.bin}
+NIMBUS_SLW_IMG = ${ENGD_OBJPATH:Fp8.ref_image.hdr.bin}
 MURANO_LOCAL_SLW_IMG = s1.ref_image.hdr.bin
 NAPLES_LOCAL_SLW_IMG = s1.ref_image.hdr.bin
 VENICE_LOCAL_SLW_IMG = p8.ref_image.hdr.bin
+NIMBUS_LOCAL_SLW_IMG = p8.ref_image.hdr.bin
 MURANO_LOCAL_SLW_IMG_ECC = s1.ref_image.hdr.bin.ecc
 NAPLES_LOCAL_SLW_IMG_ECC = s1.ref_image.hdr.bin.ecc
 VENICE_LOCAL_SLW_IMG_ECC = p8.ref_image.hdr.bin.ecc
+NIMBUS_LOCAL_SLW_IMG_ECC = p8.ref_image.hdr.bin.ecc
 MURANO_SBE_IMG = s1SbePartition.bin
 NAPLES_SBE_IMG = s1SbePartition.bin
 VENICE_SBE_IMG = p8SbePartition.bin
+NIMBUS_SBE_IMG = p8SbePartition.bin
 MURANO_SBE_IMG_ECC = s1SbePartition.bin.ecc
 NAPLES_SBE_IMG_ECC = s1SbePartition.bin.ecc
 VENICE_SBE_IMG_ECC = p8SbePartition.bin.ecc
+NIMBUS_SBE_IMG_ECC = p8SbePartition.bin.ecc
 SBEC_IMG = centSbePartition.bin
 SBEC_IMG_ECC = centSbePartition.bin.ecc
 TEMP_IMG = temp.bin
@@ -267,6 +274,7 @@ inject_ecc: build_sbe_partitions
 	cp ${MURANO_SLW_IMG} ${MURANO_LOCAL_SLW_IMG}
 	cp ${NAPLES_SLW_IMG} ${NAPLES_LOCAL_SLW_IMG}
 	cp ${VENICE_SLW_IMG} ${VENICE_LOCAL_SLW_IMG}
+	cp ${NIMBUS_SLW_IMG} ${NIMBUS_LOCAL_SLW_IMG}
 	# HBD partition
 	dd if=${${MURANO_TARG_IMG}:P} of=${TEMP_IMG} ibs=1024k conv=sync; \
 	ecc --inject ${TEMP_IMG} --output ${MURANO_TARG_IMG_ECC} --p8; \
@@ -274,6 +282,8 @@ inject_ecc: build_sbe_partitions
 	ecc --inject ${TEMP_IMG} --output ${NAPLES_TARG_IMG_ECC} --p8; \
 	dd if=${${VENICE_TARG_IMG}:P} of=${TEMP_IMG} ibs=1024k conv=sync; \
 	ecc --inject ${TEMP_IMG} --output ${VENICE_TARG_IMG_ECC} --p8; \
+	dd if=${${NIMBUS_TARG_IMG}:P} of=${TEMP_IMG} ibs=1024k conv=sync; \
+	ecc --inject ${TEMP_IMG} --output ${NIMBUS_TARG_IMG_ECC} --p8; \
 	# SBE partition
 	dd if=${${MURANO_SBE_IMG}:P} of=${TEMP_IMG} ibs=256k conv=sync; \
 	ecc --inject ${TEMP_IMG} --output ${MURANO_SBE_IMG_ECC} --p8; \
@@ -281,6 +291,8 @@ inject_ecc: build_sbe_partitions
 	ecc --inject ${TEMP_IMG} --output ${NAPLES_SBE_IMG_ECC} --p8; \
 	dd if=${${VENICE_SBE_IMG}:P} of=${TEMP_IMG} ibs=256k conv=sync; \
 	ecc --inject ${TEMP_IMG} --output ${VENICE_SBE_IMG_ECC} --p8; \
+	dd if=${${NIMBUS_SBE_IMG}:P} of=${TEMP_IMG} ibs=256k conv=sync; \
+	ecc --inject ${TEMP_IMG} --output ${NIMBUS_SBE_IMG_ECC} --p8; \
 	# SBEC partition
 	dd if=${${SBEC_IMG}:P} of=${TEMP_IMG} ibs=512k conv=sync; \
 	ecc --inject ${TEMP_IMG} --output ${SBEC_IMG_ECC} --p8; \
@@ -291,18 +303,24 @@ inject_ecc: build_sbe_partitions
 	ecc --inject ${TEMP_IMG} --output ${NAPLES_LOCAL_SLW_IMG_ECC} --p8; \
 	dd if=${${VENICE_LOCAL_SLW_IMG}:P} of=${TEMP_IMG} ibs=1024k conv=sync; \
 	ecc --inject ${TEMP_IMG} --output ${VENICE_LOCAL_SLW_IMG_ECC} --p8; \
+	dd if=${${NIMBUS_LOCAL_SLW_IMG}:P} of=${TEMP_IMG} ibs=1024k conv=sync; \
+	ecc --inject ${TEMP_IMG} --output ${NIMBUS_LOCAL_SLW_IMG_ECC} --p8; \
 	rm ${TEMP_IMG}
 
 MURANO_SECT = HBD=${MURANO_TARG_IMG_ECC},SBE=${MURANO_SBE_IMG_ECC},SBEC=${SBEC_IMG_ECC},WINK=${MURANO_LOCAL_SLW_IMG_ECC}
 NAPLES_SECT = HBD=${NAPLES_TARG_IMG_ECC},SBE=${NAPLES_SBE_IMG_ECC},SBEC=${SBEC_IMG_ECC},WINK=${NAPLES_LOCAL_SLW_IMG_ECC}
 VENICE_SECT = HBD=${VENICE_TARG_IMG_ECC},SBE=${VENICE_SBE_IMG_ECC},SBEC=${SBEC_IMG_ECC},WINK=${VENICE_LOCAL_SLW_IMG_ECC}
+NIMBUS_SECT = HBD=${NIMBUS_TARG_IMG_ECC},SBE=${NIMBUS_SBE_IMG_ECC},SBEC=${SBEC_IMG_ECC},WINK=${NIMBUS_LOCAL_SLW_IMG_ECC}
+
 
 PNOR_IMG_INFO = \
    murano.pnor:defaultPnorLayout.xml:${MURANO_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
    naples.pnor:defaultPnorLayout.xml:${NAPLES_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
    venice.pnor:defaultPnorLayout.xml:${VENICE_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
+   nimbus.pnor:defaultPnorLayout.xml:${NIMBUS_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
    ${FIPS_PNOR_INFO}
 
+
 __IMAGE_BUILD/% : .SPECTARG .PMAKE cp_hbfiles inject_ecc
 	@${MAKE:T:R} BUILD_SPECIFIC_IMAGE \
 	    "IMAGE_PARAMS=${.TARGET:s/__IMAGE_BUILD\///:s/:/ /g}"
diff --git a/src/build/simics/combined.simics b/src/build/simics/combined.simics
index 0fe3b8fbc..9d87c493c 100755
--- a/src/build/simics/combined.simics
+++ b/src/build/simics/combined.simics
@@ -20,3 +20,19 @@ try {
         }
     }
 } except { echo "ERROR: Failed to load tools in combined.simics." }
+
+# Workaround to set the sim_ctrl1 reg to enable the
+# old HPT SDR1 translation, not the new PTCR translation
+# SIM_CTRL1_P9_SDR1    0x0010000000000000
+# @todo-RTC:126640  Remove with P9 page table support
+system_cmp0.cpu0_0_00_0.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_00_1.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_00_2.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_00_3.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_0.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_1.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_2.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_3.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_00_0.disable
+
+
diff --git a/src/build/simics/hb-pnor-vpd-preload.pl b/src/build/simics/hb-pnor-vpd-preload.pl
index 9289baf26..bf1832942 100755
--- a/src/build/simics/hb-pnor-vpd-preload.pl
+++ b/src/build/simics/hb-pnor-vpd-preload.pl
@@ -290,6 +290,10 @@ sub createMVPDData
             {
                 $sourceFile = "$dataPath/$mvpdFile_p9n";
             }
+            elsif( $machine eq "ZZTOP")
+            {
+                $sourceFile = "$dataPath/$mvpdFile_p9n";
+            }
             else
             {
                 $sourceFile = "$dataPath/$mvpdFile";
@@ -521,7 +525,12 @@ sub getCentaurConfig
             elsif( $machine eq "NIMBUS")
             {
             #as there are no centaurs within a NIMBUS machine NO configuration
-            #for centaur chips is required 
+            #for centaur chips is required
+            }
+            elsif( $machine eq "ZZTOP")
+            {
+            #as there are no centaurs within a NIMBUS machine NO configuration
+            #for centaur chips is required
             }
             else
             {
diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics
index 215e80c95..9a151d02a 100755
--- a/src/build/simics/standalone.simics
+++ b/src/build/simics/standalone.simics
@@ -4,7 +4,9 @@
 
 ($hb_masterproc).proc_fsi2host_mbox->responder_enable=1
 
-# @todo-RTC:127341 Standalaone VPD support
+# @todo RTC:138068 Replace this when we get a working image
+$hb_pnor.sfc_master_mem.load-file $hb_pnor->flash_file
+
 # Preload VPD in PNOR
     try {
         run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py)
@@ -13,13 +15,11 @@
             ($hb_pnor).sfc_master_mem.load-file ./syscvpd.dat.ecc 0x255000
     } except { echo "ERROR: Failed to preload VPD into PNOR." }
 
-# Uncomment when PNOR is supported
-# @todo-RTC:130182 Enable PNOR access
 #Write the PNOR MMIO addr into Scratch 2, 0x283A
-#($hb_masterproc).proc_lbus_map.write 0x28e8 0xFFF78000  #HB PNOR addr
-#foreach $cc in (get-object-list p9_proc) {
-#    ($cc).proc_lbus_map.write 0x28e8 0xFFF78000
-#}
+($hb_masterproc).proc_lbus_map.write 0x28e8 0xFFF78000  #HB PNOR addr
+foreach $cc in (get-object-list p9_proc) {
+    ($cc).proc_lbus_map.write 0x28e8 0xFFF78000
+}
 
 # Loop through every processor chip
 foreach $cc in (get-object-list p9_proc) {
@@ -41,45 +41,19 @@ foreach $cc in (get-object-list p9_proc) {
     ($cc).proc_chip.invoke parallel_store STARTSBEREGS 0 "80000000" 32
 }
 
-# Workaround to load hb image into memory
-# @todo-RTC:130182 Remove when PNOR access enabled
-system_cmp0.phys_mem.load-file $hb_script_location+"/hbicore.bin" 0x0
-
 # Workaround to set the sim_ctrl1 reg to enable the
 # old HPT SDR1 translation, not the new PTCR translation
 # SIM_CTRL1_P9_SDR1    0x0010000000000000
 # @todo-RTC:126640  Remove with P9 page table support
 system_cmp0.cpu0_0_00_0.write-reg sim_ctrl1 0x4230000000000000
-
-# Workaround to set the hrmor
-# @todo-RTC:130184 Remove with real SBE behavior
-system_cmp0.cpu0_0_00_0.write-reg hrmor 0x0000008000000
-
-# @todo-RTC:130182 Update when PNOR is supported
-###################################
-#Configure SFC (mimmic FSP Setup)
-###################################
-#echo "Configure SFC"
-
-#foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) {
-#    echo $pnor
-#    #Direct Read window config
-#    ($pnor).sfc_master->regs_OADRNB = 0xC000000
-#    ($pnor).sfc_master->regs_ADRCBF = 0x0
-#    ($pnor).sfc_master->regs_ADRCMF = 0xF
-
-#    #Direct Access Cache Disable
-#    ($pnor).sfc_master->regs_CONF = 0x00000002
-
-#    #Small Erase op code
-#    ($pnor).sfc_master->regs_CONF4 = 0x00000020
-#    #Erase Size
-#    ($pnor).sfc_master->regs_CONF5 = 0x1000
-
-#    #Enable 4 byte address mode - must write via memory to trigger
-#    #model behavior
-#    ($pnor).fsi_local_lbus_map.write 0xC40 0x00006E00
-#}
+system_cmp0.cpu0_0_00_1.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_00_2.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_00_3.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_0.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_1.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_2.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_01_3.write-reg sim_ctrl1 0x4230000000000000
+system_cmp0.cpu0_0_00_0.enable
 
 ###################################
 #Enable the IPMI Responder
diff --git a/src/build/simics/startup.simics b/src/build/simics/startup.simics
index 7cc5887cb..19429d536 100755
--- a/src/build/simics/startup.simics
+++ b/src/build/simics/startup.simics
@@ -15,8 +15,14 @@ echo "Master Proc is: "+$hb_masterproc
 
 $hb_pnor = ""
 
-foreach $pnor in (get-object-list - all BmcCmp) {
-  $hb_pnor = ($pnor)
+@simenv.hb_pnor = quiet_run_command("get-master-pnor")[0]
+try {
+    @SIM_get_object(simenv.hb_pnor[0])
+} except {
+    # Default to Nimbus name
+    foreach $pnor in (get-object-list -all BmcCmp) {
+       $hb_pnor = ($pnor)
+    }
 }
 
 echo "Master PNOR is: "+$hb_pnor
@@ -25,12 +31,13 @@ echo "Master PNOR is: "+$hb_pnor
 $hb_cpu = "system_cmp0.cpu0_0_00_0"
 echo "Defaulting to CPU "+$hb_cpu+" for Hostboot tools"
 
+# @todo RTC 130184 Simics P9 SBE
 # Prevent SBE Updates from happening on an IPL
-echo "Altering SBE SEEPROM Versions to disable Update in IPL"
-foreach $cc in (get-object-list p9_proc) {
-    ($cc).procSBE0Primary_eeprom_image.set 0x300 0x5A5A5A5A 8 -l
-    ($cc).procSBE0Backup_eeprom_image.set  0x300 0x5A5A5A5A 8 -l
-}
+#echo "Altering SBE SEEPROM Versions to disable Update in IPL"
+#foreach $cc in (get-object-list p9_proc) {
+#    ($cc).procSBE0Primary_eeprom_image.set 0x300 0x5A5A5A5A 8 -l
+#    ($cc).procSBE0Backup_eeprom_image.set  0x300 0x5A5A5A5A 8 -l
+#}
 
 # Load HB debug tools.
 try {