Support Brazos Simics model names in debug tools

Quick fix to support the new object names in the Brazos Simics
model.  There are more changes required to support multinode
(see RTC: 61853) but this should work for single node bringup.

Change-Id: If0c591a2ae7c6665dcf76aa4a2e5a904455da4dd
RTC: 68898
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3955
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 51 insertions, 19 deletions

diff --git a/src/build/simics/combined.simics b/src/build/simics/combined.simics
index 28c1b022f..0c234e1b8 100755
--- a/src/build/simics/combined.simics
+++ b/src/build/simics/combined.simics
@@ -1,3 +1,7 @@
+# Note : Assumes these vars were setup in startup.simics
+# $hb_masterproc : name of master proc chip object
+# $hb_pnor : name of pnor object associated with master proc
+
 #If running in Hostboot Developer Environment, copies patched base 
 #and extended hostboot images onto the FSP so HWSV will load 
 #pached versions to PNOR instead of the default images 
@@ -25,12 +29,12 @@ try {
 # Only needed in combined configs to enable FSP communication.  Hostboot
 # PNOR DD covers hostboot access.  Remove with RTC: 51500
 try {
-    fpga0.sfc_master->state_three_bytes=0
+    ($hb_pnor).sfc_master->state_three_bytes=0
 } except { echo "ERROR: Failed to run 4-byte PNOR address workaround in combined.simics." }
 
 # Manually set HB location till HWSV RTC 48188 is done
 try {
-    p8Proc0.proc_lbus_map.write 0x28e8 0xFFEF0000
+    ($hb_masterproc).proc_lbus_map.write 0x28e8 0xFFEF0000
 } except { echo "ERROR: Failed to set HB MMIO location workaround in combined.simics." }
 
 
diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics
index 646039d78..c4978afd4 100755
--- a/src/build/simics/standalone.simics
+++ b/src/build/simics/standalone.simics
@@ -1,23 +1,28 @@
-p8Proc0.proc_fsi2host_mbox->responder_enable=1
+# Note : Assumes these vars were setup in startup.simics
+# $hb_masterproc : name of master proc chip object
+# $hb_pnor : name of pnor object associated with master proc
+
+($hb_masterproc).proc_fsi2host_mbox->responder_enable=1
 
 # Preload VPD in PNOR
 try {
     run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py)
-    fpga0.sfc_master_mem.load-file ./sysmvpd.dat 0x3E0A000
-    fpga0.sfc_master_mem.load-file ./sysspd.dat 0x3DCA000
-    fpga0.sfc_master_mem.load-file ./syscvpd.dat 0x3E8A000
+    ($hb_pnor).sfc_master_mem.load-file ./sysmvpd.dat 0x3E0A000
+    ($hb_pnor).sfc_master_mem.load-file ./sysspd.dat 0x3DCA000
+    ($hb_pnor).sfc_master_mem.load-file ./syscvpd.dat 0x3E8A000
 } except { echo "ERROR: Failed to preload VPD into PNOR." }
 
 #Trigger a power on to cec-chip
-@SIM_get_interface(conf.p8Proc0.proc_chip, "signal").signal_raise(conf.p8Proc0.proc_chip)
+@mp="%s.proc_chip"%simenv.hb_masterproc
+@SIM_get_interface(SIM_get_object(mp),"signal").signal_raise(SIM_get_object(mp))
 
 #Write the PNOR MMIO addr into Scratch 2, 0x283A 
 #Then trigger the flush, load, and SBE start 
-p8Proc0.proc_lbus_map.write 0x28e8 0xFFEF0000  #HB PNOR addr
-p8Proc0.proc_lbus_map.write 0x28e0 0x0000FBFF  #NonFunc EX (only 5 is good)
-p8Proc0.proc_lbus_map.write 0x2848 0x00000FFF  #GP3 0x2812 (flush) 
-p8Proc0.proc_lbus_map.write 0x2870 0x10000000  #SBE Vital 0x281C (load) 
-p8Proc0.proc_lbus_map.write 0x2870 0x90000000  #SBE Vital 0x281C (start)
+($hb_masterproc).proc_lbus_map.write 0x28e8 0xFFEF0000  #HB PNOR addr
+($hb_masterproc).proc_lbus_map.write 0x28e0 0x0000FBFF  #NonFunc EX (only 5 is good)
+($hb_masterproc).proc_lbus_map.write 0x2848 0x00000FFF  #GP3 0x2812 (flush) 
+($hb_masterproc).proc_lbus_map.write 0x2870 0x10000000  #SBE Vital 0x281C (load) 
+($hb_masterproc).proc_lbus_map.write 0x2870 0x90000000  #SBE Vital 0x281C (start)
 
 ###################################
 #Configure SFC (mimmic FSP Setup)
@@ -25,18 +30,18 @@ p8Proc0.proc_lbus_map.write 0x2870 0x90000000  #SBE Vital 0x281C (start)
 echo "Configure SFC"
 
 #Direct Read window config
-fpga0.sfc_master->regs_OADRNB = 0xC000000
-fpga0.sfc_master->regs_ADRCBF = 0x0
-fpga0.sfc_master->regs_ADRCMF = 0xF
+($hb_pnor).sfc_master->regs_OADRNB = 0xC000000
+($hb_pnor).sfc_master->regs_ADRCBF = 0x0
+($hb_pnor).sfc_master->regs_ADRCMF = 0xF
 
 #Direct Access Cache Disable 
-fpga0.sfc_master->regs_CONF = 0x00000002
+($hb_pnor).sfc_master->regs_CONF = 0x00000002
 
 #Small Erase op code
-fpga0.sfc_master->regs_CONF4 = 0x00000020
+($hb_pnor).sfc_master->regs_CONF4 = 0x00000020
 #Erase Size
-fpga0.sfc_master->regs_CONF5 = 0x1000
+($hb_pnor).sfc_master->regs_CONF5 = 0x1000
 
 #Enable 4 byte address mode - must write via memory to trigger 
 #model behavior
-fpga0.fsi_local_lbus_map.write 0xC40 0x00006E00
+($hb_pnor).fsi_local_lbus_map.write 0xC40 0x00006E00
diff --git a/src/build/simics/startup.simics b/src/build/simics/startup.simics
index de0efe92c..fbd7d0f19 100755
--- a/src/build/simics/startup.simics
+++ b/src/build/simics/startup.simics
@@ -7,6 +7,29 @@ $hb_machine = (shell "env | grep 'GFW_P8_.*_PROC_CCIN' | sed 's/GFW_P8_\\(.*\\)_
 $hb_machine = (python "\""+$hb_machine+"\".lower()")
 python "os.environ['HB_MACHINE'] = \""+$hb_machine+"\""
 
+
+# Setup some common vars to use across machine types
+$hb_masterproc = ""
+try {
+    # Attempt to use the Brazos name
+    @SIM_get_object("cecdrawer0_p8Proc0")
+    $hb_masterproc = "cecdrawer0_p8Proc0"
+} except {
+    # Default to Tuleta/Orlena name
+    $hb_masterproc = "p8Proc0"
+}
+
+$hb_pnor = ""
+try {
+    # Attempt to use the Brazos name
+    @SIM_get_object("cecdrawer0_fpga0")
+    $hb_pnor = "cecdrawer0_fpga0"
+} except {
+    # Default to Tuleta/Orlena name
+    $hb_pnor = "fpga0"
+}
+
+
 # Load HB debug tools.
 try {
     run-python-file (lookup-file hbfw/simics-debug-framework.py)